Datasheet > MSM548263-70TS-K

MSM548263-70TS-K

更新时间： 2024-01-03 11:25:16

品牌	Logo	应用领域
冲电气 - OKI		动态存储器光电二极管内存集成电路
页数	文件大小	规格书
40页	392K
描述
Video DRAM, 256KX8, 70ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40

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MSM548263-70TS-K 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2, TSOP40/44,.46,32
针数：	44	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.58	访问模式：	FAST PAGE WITH EDO
最长访问时间：	70 ns	其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH; 512 X 8 SAM PORT
JESD-30 代码：	R-PDSO-G40	JESD-609代码：	e0
长度：	18.41 mm	内存密度：	2097152 bit
内存集成电路类型：	VIDEO DRAM	内存宽度：	8
功能数量：	1	端口数量：	2
端子数量：	40	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装等效代码：	TSOP40/44,.46,32
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大待机电流：	0.008 A	子类别：	Other Memory ICs
最大压摆率：	0.13 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm	Base Number Matches：	1

MSM548263-70TS-K 数据手册

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¡ Semiconductor

MSM548263

Read Transfer: RAS falling edge --- CAS = WE = "H", TRG = DSF = "L"

Read transfer consists of loading a selected row of data from the RAM into the SAM register. A

read transfer is invoked by holding CAS "high", TRG "low", WE "high", and DSF "low" at the

fallingedgeofRAS. TherowaddressselectedatthefallingedgeofRASdeterminestheRAMrow

to be transferred into the SAM. The transfer cycle is completed at the rising edge of TRG. When

the transfer is completed, the SAM port is set into the output mode. In a read/real time read

transfer cycle, the transfer of a new row of data is completed at the rising edge of TRG, and this

data becomes valid on the SDQ lines after the specified access time t

from the rising edge of

SCA

the subsequent SC cycles. The start address of the serial pointer of the SAM is determined by the

column address selected at the falling edge of CAS. In a read transfer cycle (which is preceded

by a write transfer cycle), SC clock must be held at a constant V or V after the SC high time

has been satisfied. A rising edge of the SC clock must not occur until after the specified delay t

TSD

from the rising edge of TRG.

In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous

row data appears on the SDQ lines until the TRG signal goes "high", and the serial access time

for the following serial clock is satisfied. This feature allows for the first bit of the new row

SCA

of data to appear on the serial output as soon as the last bit of the previous row has been strobed

withoutanytimingloss. Tomakethiscontinuousdataflowpossible, therisingedgeofTRGmust

besynchronizedwithRAS, CAS, andthesubsequentrisingedgeofSC(t

, t

, andt /t

RTH CTH TSL TSD

must be satisfied).

Masked Write Transfer: RAS falling edge --- CAS = "H", TRG = WE = DSF = "L"

Write transfer cycle consists of loading the content of the SAM register into a selected row of the

RAM. This write transfer is the same as a mask write operation in RAM, so new and persistent

(old) mask mode can be supported. (Masked write transfer)

If the SAM data to be transferred must first be loaded through the SAM, a Masked write transfer

operation (all DQ pins "low" at falling edge of RAS) must precede the write transfer cycles. A

masked write transfer is invoked by holding CAS "high", TRG "low", WE "low" and DSF "low"

at the falling edge of RAS. The row address selected at the falling edge of RAS determines the

RAM row address into which the data will be transferred. The column address selected at the

falling edge of CAS determines the start address of the serial pointer of the SAM. After the write

transfer is completed, the SDQ lines are set in the input mode so that serial data synchronized

with the SC clock can be loaded.

When consecutive write transfer operations are performed, new data must not be written into

the serial register until the RAScycle of the preceding write transfer is completed. Consequently,

the SC clock must be held at a constant V or V during the RAS cycle. A rising edge of the SC

clockisonlyallowedafterthespecifieddelayt

a new row of data can be written in the serial register.

fromthefallingedgeoftheCAS, atwhichtime

CSD

Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to the

other address of RAM by write transfer cycle. However, the address to write data must be the

same as that of the read transfer cycle (row address AX8).

35/40

1...32 33 343536 37 38...40

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STM32F103C8T6 替代型号

型号	品牌	替代类型	描述	数据表

与MSM548263-70TS-K相关器件

型号	品牌	描述	获取价格	数据表
MSM548263-80TS-K	OKI	Video DRAM, 256KX8, 80ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40	获取价格
MSM548331	OKI	222,720-Word x 12-Bit Field Memory	获取价格
MSM548332	OKI	278,400-Word x 12-Bit Field Memory	获取价格
MSM548333	OKI	240,384-Word x 8-bit + 240,384-Word x 4-bit Triple Port type Field Memory	获取价格
MSM548512D-10GS	OKI	Pseudo Static RAM, 512KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SSOP-32	获取价格
MSM548512D-10RS	OKI	Pseudo Static RAM, 512KX8, 100ns, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	获取价格

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