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MSM51V8222A-30JS PDF预览

MSM51V8222A-30JS

更新时间: 2024-10-03 03:35:03
品牌 Logo 应用领域
冲电气 - OKI 光电二极管内存集成电路
页数 文件大小 规格书
17页 200K
描述
Memory Circuit, 256KX8, CMOS, PDSO28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-28

MSM51V8222A-30JS 数据手册

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E2L0055-28-Z2  
This version: Dec. 1998  
Previous version: Mar. 1998  
¡ Semiconductor  
MSM51V8222A  
262,214-Word ¥ 8-Bit Field Memory  
DESCRIPTION  
The OKI MSM51V8222A is a high performance 2-Mbit, 256K ¥ 8-bit, Field Memory. It is designed  
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital  
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity  
TVs and VTRs, exclusively. The MSM51V8222A is not designed for the other use or high end  
use in medical systems, professional graphics systems which require long term picture, and  
data storage systems and others. The 2-Mbit capacity fits one field of a conventional NTSC TV  
screen. TwocascadedMSM51V8222Asmakeoneframeofthescreen:twoormoreMSM51V8222As  
can be cascaded directly without any delay devices between them. (Cascading provides larger  
storage depth or a longer delay).  
Each of the 8-bit planes has separate serial write and read ports. These employ independent control  
clockstosupportasynchronousreadandwriteoperations. Differentclockratesarealsosupported,  
which allow alternate data rates between write and read data streams.  
The MSM51V8222A provides high speed FIFO, First-In First-Out, operation without external  
refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.  
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial  
access operation, so that serial read and/or write control clock can be halted high or low for any  
duration as long as the power is on. Internal conflicts of memory access and refreshing operations  
are prevented by special arbitration logic.  
TheMSM51V8222A'sfunctionissimple,andsimilartoadigitaldelaydevicewhosedelay-bit-length  
is easily set by reset timing. The delay length, and the number of read delay clocks between write  
and read, is determined by externally controlled write and read reset timings.  
AdditionalSRAMserialregisters, orlinebuffersfortheinitialaccessof256¥8-bitenablehighspeed  
first-bit-access with no clock delay just after the write or read reset timings.  
The MSM51V8222A is similar in operation and functionality to OKI 1-Mbit Field Memory  
MSM51V4221C, with the addition of cascade capability. (As for MSM51V4221C operation  
compatible 2-Mbit Field Memory, OKI has the MSM51V8221A which is a sister device of  
MSM51V8222A).  
Additionally, the MSM51V8222A has a write mask function or input enable function (IE), and read-  
data skipping function or output enable function (OE). The differences between write enable (WE)  
andinputenable(IE), andbetweenreadenable(RE)andoutputenable(OE)arethatWEandREcan  
stop serial write/read address increments, but IE and OE cannot stop the increment, when write/  
read clocking is continuously applied to MSM51V8222A. The input enable (IE) function allows the  
user to write into selected locations of the memory only, leaving the rest of the memory contents  
unchanged. This facilitates data processing to display a "picture in picture" on a TV screen.  
1/16  

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