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MSC1214Y5PAGR

更新时间: 2024-01-06 08:19:00
品牌 Logo 应用领域
德州仪器 - TI 转换器闪存微控制器
页数 文件大小 规格书
105页 912K
描述
Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory

MSC1214Y5PAGR 数据手册

 浏览型号MSC1214Y5PAGR的Datasheet PDF文件第97页浏览型号MSC1214Y5PAGR的Datasheet PDF文件第98页浏览型号MSC1214Y5PAGR的Datasheet PDF文件第99页浏览型号MSC1214Y5PAGR的Datasheet PDF文件第101页浏览型号MSC1214Y5PAGR的Datasheet PDF文件第102页浏览型号MSC1214Y5PAGR的Datasheet PDF文件第103页 
ꢀ ꢁ ꢂꢃ ꢄ ꢃꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢃ ꢄ  
ꢀ ꢁ ꢂꢃ ꢄ ꢃ ꢆꢅ ꢀ ꢁꢂ ꢃꢄ ꢃ ꢇ  
www.ti.com  
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005  
Seconds Timer Interrupt (SECINT)  
7
6
5
4
3
2
1
0
Reset Value  
SFR F9h  
WRT  
SECINT6  
SECINT5  
SECINT4  
SECINT3  
SECINT2  
SECINT1  
SECINT0  
7Fh  
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the  
register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate  
an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt; however, AI  
in EICON (SFR D8h) must also be cleared. This Interrupt can be monitored in the AIE or AIPOL registers.  
WRT  
Write Control. Determines whether to write the value immediately or wait until the current count is finished.  
Read = 0.  
bit 7  
0 = Delay Write Operation. The SEC value is loaded when the current count expires.  
1 = Write Immediately. The counter is loaded once the CPU completes the write operation.  
SECINT6−0 Seconds Count. Normal operation would use 100ms as the clock interval.  
bits 6−0 Seconds Interrupt = (1 + SEC) (HMSEC + 1) (MSEC + 1) t  
.
CLK  
Milliseconds Timer Interrupt (MSINT)  
7
6
5
4
3
2
1
0
Reset Value  
SFR FAh  
WRT  
MSINT6  
MSINT5  
MSINT4  
MSINT3  
MSINT2  
MSINT1  
MSINT0  
7Fh  
The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers  
MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also  
be cleared.  
WRT  
Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.  
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.  
bit 7  
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.  
MSINT6−0 Milliseconds Count. Normal operation would use 1ms as the clock interval.  
bits 6−0 MS Interrupt Interval = (1 + MSINT) (MSEC + 1) t  
CLK  
One Microsecond Timer (USEC)  
7
6
5
4
3
2
1
0
Reset Value  
SFR FBh  
0
0
FREQ5  
FREQ4  
FREQ3  
FREQ2  
FREQ1  
FREQ0  
03h  
FREQ5−0 Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs Clock.  
bits 5−0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh).  
One Millisecond Timer Low Byte (MSECL)  
7
6
5
4
3
2
1
0
Reset Value  
SFR FCh  
MSECL7  
MSECL6  
MSECL5  
MSECL4  
MSECL3  
MSECL2  
MSECL1  
MSECL0  
9Fh  
MSECL7−0 One Millisecond Timer Low Byte. This value in combination with the next register is used to create a 1ms clock.  
bits 7−0  
1ms = (MSECH 256 + MSECL + 1) t  
. This clock is used to set Flash erase time. See FTCON (SFR EFh).  
CLK  
100  

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