MSC1214Y5PAGR

更新时间： 2024-01-28 12:40:32

品牌	Logo	应用领域
德州仪器 - TI		转换器闪存微控制器
页数	文件大小	规格书
105页	912K
描述
Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory

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MSC1214Y5PAGR 数据手册

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ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢇ

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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005

One Millisecond Timer High Byte (MSECH)

Reset Value

SFR FDh

MSECH7

MSECH6

MSECH5

MSECH4

MSECH3

MSECH2

MSECH1

MSECH0

0Fh

MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock.

bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • t

CLK

One Hundred Millisecond Timer (HMSEC)

Reset Value

SFR FEh

WRT

HMSEC6

HMSEC5

HMSEC4

HMSEC3

HMSEC2

HMSEC1

HMSEC0

63h

WRT

bit 7

Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.

0 = Delay Write Operation. The MSINT value is loaded when the current count expires.

1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.

HMSEC6−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock.

bits 6−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • t

CLK

Watchdog Timer (WDTCON)

Reset Value

SFR FFh

EWDT

DWDT

RWDT

WDCNT4

WDCNT3

WDCNT2

WDCNT1

WDCNT0

00h

EWDT

Enable Watchdog (R/W).

bit 7

Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.

DWDT

Disable Watchdog (R/W).

bit 6

Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.

RWDT

Reset Watchdog (R/W).

bit 5

Write 1/Write 0 sequence restarts the Watchdog Counter.

WDCNT4−0 Watchdog Count (R/W).

bits 4−0

Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is

an uncertainty of 1 count.

101

1...98 99 100101102 103 104 105

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