Datasheet > MSA24

MSA24

更新时间： 2024-01-16 05:46:31

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
7页	79K
描述
Octal Registered Transceiver

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数据手册

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MSA24 数据手册

April 1988

Revised October 2000

74F543

Octal Registered Transceiver

General Description

Features

The F543 octal transceiver contains two sets of D-type

latches for temporary storage of data flowing in either

direction. Separate Latch Enable and Output Enable inputs

are provided for each register to permit independent con-

trol of inputting and outputting in either direction of data

flow. The A outputs are guaranteed to sink 24 mA while the

B outputs are rated for 64 mA.

■ 8-bit octal transceiver

■ Back-to-back registers for storage

■ Separate controls for data flow in each direction

■ A outputs sink 24 mA

■ B outputs sink 64 mA

Ordering Code:

Order Number Package Number

Package Description

74F543SC

74F543MSA

74F543PC

74F543SPC

M24B

MSA24

N24A

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

N24C

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009554

www.fairchildsemi.com

12 3 4 5 6 7

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