Datasheet > MS8104160A

MS8104160A

更新时间： 2024-01-05 20:52:39

品牌	Logo	应用领域
冲电气 - OKI		先进先出芯片
页数	文件大小	规格书
24页	176K
描述
Dual FIFO (262,214 Words 】 8 Bits) 】 2

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MS8104160A 数据手册

FEDS8104160A-01

This version: Nov. 21, 2002

OKI Semiconductor

MS8104160A

Dual FIFO (262,214 Words × 8 Bits) × 2

GENERAL DESCRIPTION

The MS8104160A is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO (First-In First-Out)

memories which were designed for 262,214 x 8-bit high-speed asynchronous read/write operation.

The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in common. The

MS8104160A, functionally compatible with Oki's 2Mb FIFO memory (MSM518222A), can be used as a x16

configuration FIFO.

The MS8104160A is a field memory for wide or low end use in general commodity TVs and VTRs exclusively

and is not designed for high end use in professional graphics systems, which require long term picture storage, data

storage, medical use and other storage systems.

The MS8104160A provides independent control clocks to support asynchronous read and write operations.

Different clock rates are also supported, which allow alternate data rates between write and read data streams.

The MS8104160A provides high speed FIFO (First-in First-out) operation without external refreshing:

MS8104160A refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access

operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the

power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration

logic.

The MS8104160A’s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by

reset timing. The delay length and the number of read delay clocks between write and read, is determined by

externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 71 x 16-bit enable high speed

first-bit-access with no clock delay just after the write or read reset timings.

Additionally, the MS8104160A has a write mask function or input enable function (IE), and read- data skipping

function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and

between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address

increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to

MS8104160A. The input enable (IE) function allows the user to write into selected locations of the memory only,

leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture”

on a TV screen.

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与MS8104160A相关器件

型号	品牌	获取价格	描述	数据表
MS8104160A-20TB	OKI	获取价格	FIFO, 256KX8, 18ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS8104160A-25TB	OKI	获取价格	FIFO, 256KX8, 22ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS8104160A-XXTB	OKI	获取价格	Dual FIFO (262,214 Words 】 8 Bits) 】 2
MS8104160XXTB	OKI	获取价格	(262,214-word x 8-Bits) x 2 Dual FIFO
MS8104166	OKI	获取价格	Dual FIFO (262,214 Words × 8 Bits) × 2
MS8104166-20TB	OKI	获取价格	FIFO, 256KX8, 18ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS8104166-25TB	OKI	获取价格	FIFO, 256KX8, 22ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS8104166A	OKI	获取价格	Dual FIFO (262,214 Words × 8 Bits) × 2
MS8104166A-20TB	OKI	获取价格	FIFO, 256KX8, 18ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS8104166A-25TB	OKI	获取价格	FIFO, 256KX8, 22ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1

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