Datasheet > MR82C37AB

MR82C37AB

更新时间： 2024-01-14 07:02:01

品牌	Logo	应用领域
英特矽尔 - INTERSIL		控制器
页数	文件大小	规格书
23页	150K
描述
CMOS High Performance Programmable DMA Controller

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技术参数
数据手册

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MR82C37AB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QCCN, LCC44,.65SQ	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.2.C	HTS代码：	8542.31.00.01
风险等级：	5.78	地址总线宽度：	16
总线兼容性：	80C286; 80286; 80186; 80C86; 8086; 80C88; 8088; 8085; Z80; NSC800	最大时钟频率：	8 MHz
外部数据总线宽度：	8	JESD-30 代码：	S-CQCC-N44
JESD-609代码：	e0	DMA 通道数量：	4
端子数量：	44	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装等效代码：	LCC44,.65SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	5 V	认证状态：	Not Qualified
筛选级别：	38535Q/M;38534H;883B	子类别：	DMA Controllers
最大压摆率：	16 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	uPs/uCs/外围集成电路类型：	DMA CONTROLLER
Base Number Matches：	1

MR82C37AB 数据手册

82C37A

Pin Description

SYMBOL

NUMBER

TYPE

DESCRIPTION

: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for

decoupling.

GND

CLK

Ground

CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A

operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for

the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for

standby operation.

CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for

CPU communications.

RESET

RESET: This is an active high input which clears the Command, Status, Request, and Temporary

registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore

requests. Following a Reset, the controller is in an idle cycle.

READY

HLDA

READY: This signal can be used to extend the memory read and write pulses from the 82C37A to

accommodate slow memories or I/O devices. READY must not make transitions during its speciﬁed

set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.

HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has

relinquished control of the system busses. HLDA is a synchronous input and must not transition

during its speciﬁed set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising

edge of CLK, during which time HLDA must not transition.

DREQ0-

DREQ3

16-19

DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request

inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest

priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a

channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is

programmable. RESET initializes these lines to active high. DREQ must be maintained until the

corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused

DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.

DB0-DB7

21-23

26-30

I/O

DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data

bus. The outputs are enabled in the Program condition during the I/O Read to output the contents

of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle

when the CPU is programming the 82C37A control registers. During DMA cycles, the most signiﬁ-

cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.

In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during

the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write

the data into the new memory location.

IOR

I/O

I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control

signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.

IOW

I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output

control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.

4-194

1 234 5 6 7...23

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