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MPC860UM PDF预览

MPC860UM

更新时间: 2024-01-27 13:50:18
品牌 Logo 应用领域
飞思卡尔 - FREESCALE /
页数 文件大小 规格书
80页 2125K
描述
Hardware Specifications

MPC860UM 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:357
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.74地址总线宽度:32
边界扫描:YES总线兼容性:PCMCIA
数据编码/解码方法:NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER); DIFF BIPH-LEVEL最大数据传输速率:1.25 MBps
外部数据总线宽度:32JESD-30 代码:S-PBGA-B357
低功率模式:YES串行 I/O 数:4
端子数量:357封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
标称供电电压:3.3 V表面贴装:YES
技术:CMOS端子形式:BALL
端子位置:BOTTOMuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

MPC860UM 数据手册

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Features  
Table 1. MPC860 Family Functionality  
Cache (Kbytes) Ethernet  
Part  
ATM  
SCC  
Reference 1  
Instruction  
Cache  
Data Cache  
10T  
10/100  
MPC860DE  
MPC860DT  
MPC860DP  
MPC860EN  
MPC860SR  
MPC860T  
4
4
4
4
8
4
4
4
8
4
Up to 2  
Up to 2  
Up to 2  
Up to 4  
Up to 4  
Up to 4  
Up to 4  
1
1
2
2
2
4
4
4
4
1
1
1
1
1
1
1
1
2
Yes  
Yes  
16  
4
1
1
4
Yes  
Yes  
Yes  
Yes  
4
MPC860P  
MPC855T  
16  
4
1
1
1
Supporting documentation for these devices refers to the following:  
1. MPC860 PowerQUICC Family User’s Manual (MPC860UM, Rev. 3)  
2. MPC855T User’s Manual (MPC855TUM/D, Rev. 1)  
2 Features  
The following list summarizes the key MPC860 features:  
TM  
Embedded single-issue, 32-bit PowerPC core (implementing the PowerPC architecture) with  
thirty-two 32-bit general-purpose registers (GPRs)  
— The core performs branch prediction with conditional prefetch without conditional execution.  
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)  
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches  
are two-way, set-associative with 128 sets.  
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way,  
set-associative with 128 sets.  
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache  
blocks.  
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and  
are lockable on a cache block basis.  
— MMUs with 32-entry TLB, fully-associative instruction, and data TLBs  
— MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual address spaces  
and 16 protection groups  
— Advanced on-chip-emulation debug mode  
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)  
32 address lines  
Operates at up to 80 MHz  
Memory controller (eight banks)  
— Contains complete dynamic RAM (DRAM) controller  
MPC860 Family Hardware Specifications, Rev. 7  
2
Freescale Semiconductor  

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