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MP7651AN PDF预览

MP7651AN

更新时间: 2024-11-21 10:49:51
品牌 Logo 应用领域
艾科嘉 - EXAR 解码器转换器数模转换器
页数 文件大小 规格书
20页 223K
描述
8-Channel, Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Data Port and Chip Select Decoder

MP7651AN 数据手册

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MP7651  
8-Channel, Voltage Output  
10 MHz Input Bandwidth 8-Bit Multiplying  
DACs with Serial Digital Data Port  
and Chip Select Decoder  
FEATURES  
Low Harmonic Distortion: 0.25% typical  
8 Independent 2-Quadrant Multiplying 8-Bit DACs  
Serial Digital Input Data and Address Port (3-Wire  
Standard) plus Internal Chip Address Decoder  
Dual Supplies (+5 V typ.)  
with V  
= 1 V p-p @ 1 MHz  
REF  
V /2 Output Preset Level  
REF  
Latch-Up Proof  
High Speed:  
Greater than 2000 V ESD Protection  
12.5 MHz Digital Clock Rate  
to V Settling Time: 150ns to  
8-bit (typ)  
V
REF  
OUT  
APPLICATIONS  
Voltage Reference Input Bandwidth:  
10 MHz (typ)  
ATE  
Process Control (Low Noise)  
Convergence Adjustment for High  
Resolution Monitors (Work Stations)  
Digital Gain/Attenuation/Offset Control  
Trimmer Replacement  
Low Power: 150mW (typ)  
Low AC Voltage Reference Feedthrough  
Excellent Channel-to-Channel Isolation  
DNL = +0.8 LSB, INL = +1 LSB (typ)  
DACs Matched to +0.5% (typ)  
GENERAL DESCRIPTION  
The MP7651 is ideal for direct gain control of video, compos-  
ite video, CCDandotherhighfrequencyanalogsignals. Thede-  
vice includes 8-channels of high speed, high bandwidth, two  
quadrant, multiplying, 8-bit accurate digital-to-analog converter.  
It includes an output drive buffer per channel capable of driving  
+1mA (typ) to a load. DNL of better than +0.8 LSB is achieved  
with a channel-to-channel matching of better than 0.5%. Stabil-  
ity, matching, and precision of the DACs is achieved by using  
EXAR’sthinfilmtechnology. Also, excellentchannel-to-channel  
isolation is achieved with EXAR’s BiCMOS process which can-  
not be achieved using a typical CMOS technology.  
fast output settling time, and VREF feedthrough isolation of  
–65dB or better. In addition, low distortion in the order of 0.25%  
with a 1 V p–p, 1 MHz signal.  
A specified and constant input impedance of each VREF+ in-  
put gives flexibility for optimal system design. The serial data  
3-wire standard µ-processor logic interface reduces pin count,  
package size (28 pin), and board wire (space). Additionally, the  
internal chip select decoder allows for easy daisy chaining with-  
out the addition of separate control logic.  
MP7651 is fabricated on a junction isolated, high speed, dual  
metal,linearcompatibleBiCMOS(BiCMOSIVTM)thinfilmresis-  
tors. This process enables precision high speed analog/digital  
(mixed-mode) circuits to be fabricated on the same chip.  
An open loop architecture (patent pending) provides wide  
small signal bandwidth from VREF to output up to 10 MHz (typ),  
Rev. 2.00  
1

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