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MP1230ABS PDF预览

MP1230ABS

更新时间: 2024-11-18 04:14:51
品牌 Logo 应用领域
艾科嘉 - EXAR 转换器微处理器
页数 文件大小 规格书
12页 114K
描述
CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter

MP1230ABS 数据手册

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MP1230A/31A/32A  
CMOS Microprocessor Compatible  
Double-Buffered 12-Bit  
Digital-to-Analog Converter  
FEATURES  
Superior Ruggedized 1230 Series: 2 KV ESD  
Four Quadrant Multiplication  
Lower Data Bus Feedthrough @ CS = 1  
V from +11 V to +16 V  
DD  
Stable, More Accurate Segmented DAC Approach  
Latch-Up Free CMOS Technology  
12-Bit Bus Version: MP1208/1209/1210  
16-Bit Upgrade: MP7636A  
0.2 ppm/°C Linearity Tempco  
2 ppm/°C Max Gain Error Tempco  
Lowest Sensitivity to Amplifier Offset  
Lowest Output Capacitance (C  
Lower Glitch Energy  
= 80pF)  
OUT  
Monotonic over Temperature Range  
GENERAL DESCRIPTION  
The MP1230A series are superior pin for pin replacements  
for the 1230 series. The MP1230A series is manufactured using  
advanced thin film resistors on a double metal CMOS process  
which promotes significant improvements in reliability, latch-up  
free performance and ESD protection.  
temperature ranges. Scale factor tempco is a low 2 ppm/°C  
maximum.  
Low Output Capacitance: Due to smaller MOSFET switch  
geometries allowed by decoding, the output capacitance at  
IOUT1 and IOUT2 is a low 80pF / 40pF and 25pF / 65 pF. This  
less than half the competitive DAC 1230 series. Lower ca-  
pacitance allows the MP1230A series to achieve settling  
times faster than 1 µs for a 10 V step.  
The MP1230A series incorporates a unique decoding tech-  
nique yielding lower glitch, higher speed and excellent accuracy  
over temperature and time. 12-bit linearity is achieved without  
trimming. Outstanding features include:  
Low Sensitivity to Output Amplifier Offset: The linearity er-  
rorcausedbyamplifieroffsetisreducedbyafactorof2inthe  
MP1230A series over conventional R-2R DACs.  
Stability: integral and differential linearity tempcos are rated  
The MP1230A series uses a circuit which reduces transients  
at 0.2 ppm/°C typical. Monotonicity is guaranteed over all  
in the supplies caused by DATA bus transitions at  
= 1.  
CS  
SIMPLIFIED BLOCK DIAGRAM  
V
DD  
V
REF  
INPUT LATCH  
DAC LATCH  
R
FB  
DB11-DB4  
DB3-DB0  
D
Q
D
Q
I
OUT1  
8
8
V
REF  
8
12  
BYTE1/BYTE2  
I
LE  
LE  
OUT2  
D
Q
12  
4
4
CS  
WR1  
LE  
DGND  
AGND  
XFER WR2  
Rev. 2.00  
1

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