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MN101DF09GAF PDF预览

MN101DF09GAF

更新时间: 2024-11-15 13:11:43
品牌 Logo 应用领域
松下 - PANASONIC 微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
5页 323K
描述
Microcontroller, 8-Bit, FLASH, MN101C00 CPU, 14.32MHz, CMOS, PQFP100, 18 X 18 MM, LEAD FREE, PLASTIC, QFP-100

MN101DF09GAF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:18 X 18 MM, LEAD FREE, PLASTIC, QFP-100针数:100
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.78具有ADC:YES
其他特性:ALSO OPERATES AT 2.5V MINIMUM SUPPLY地址总线宽度:
位大小:8CPU系列:MN101C00
最大时钟频率:14.32 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:S-PQFP-G100长度:18 mm
I/O 线路数量:57端子数量:100
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.9SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/5 V
认证状态:Not QualifiedRAM(字节):4096
ROM(单词):131072ROM可编程性:FLASH
座面最大高度:2.85 mm速度:14.32 MHz
子类别:Microcontrollers最大压摆率:100 mA
最大供电电压:5.5 V最小供电电压:2.7 V
标称供电电压:5 V表面贴装:YES
技术:CMOS端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:18 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

MN101DF09GAF 数据手册

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MN101D09E  
Type  
MN101D09E  
Mask ROM  
80K  
MN101DF09G  
FLASH  
128K  
Internal ROM type  
ROM (byte)  
RAM (byte)  
2K  
4K  
Package (Lead-free)  
QFP100-P-1818B  
[With main clock operated]  
0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz)  
71.5 µs (at 2.7 V to 5.5 V, 14.32 MHz internal  
frequency di Vision)  
0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz)  
71.5 µs (at 2.7 V to 5.5 V, 14.32 MHz internal  
frequency di Vision)  
Minimum Instruction  
Execution Time  
[When sub-clock operated]  
61 µs (at 2.5 V to 5.5 V, 32.768 kHz)  
61 µs (at 2.5 V to 5.5 V, 32.768 kHz)  
Interrupts  
RESET, Runaway, External 0 to 4, Timer 0 to 3, Timer 6, Capstan FG, Control, HSW, Cylinder(Drum) FG, Servo V-sync,  
Synchronous output, OSD, XDS, Serial 1, Serial 2, PWM 4, OSD V-sync  
Timer Counter  
Timer counter 0 : 8-bit × 1 (timer function)  
Clock source................ 1/4, 1/16 of system clock frequency  
Interrupt source ........... overflow of timer counter 0  
Timer counter 1 : 8-bit × 1 (timer function, linear timer counter function)  
Clock source................ 1/4 of system clock frequency; CTL signal  
Interrupt source ........... overflow of timer counter 1  
Timer counter 2 : 16-bit × 1 (timer function, input capture (CTL specified edge), duty judgment of CTL signal)  
Clock source................ 1/4, 1/16, 1/24 of system clock frequency  
Interrupt source ........... overflow of timer counter 2; input of CTL specified edge; underflow of timer 2 shift register 4-bit counter;  
coincidence of timer 2 shift register with timer 2 shift register compare register  
Timer counter 3 : 16-bit × 1 (timer function)  
Clock source................ 1/4, 1/16 of system clock frequency  
Interrupt source ........... overflow of timer counter 3  
Timer counter 5 : 19-bit × 1 (watchdog, stable oscillation waiting function)  
Clock source................ system clock  
Watchdog interrupt source... 1/216, 1/219 of timer counter 5 frequency  
Clear by stable oscillation ... after 256 counts by timer counter 5 (218 counts of OSC oscillation clock)  
Timer counter 6 : 16-bit × 1 (clock function [max. 2 s])  
Clock source................ 1/512 of OSC oscillation clock frequency; XI oscillation clock; 1/8, 1/128 of system clock frequency  
Interrupt source ........... 1/213, 1/214, 1/215 overflow of timer counter 6  
Serial interface  
Serial 1 : 8-bit × 1 (synchronous type)  
(transfer direction of MSB/LSB selectable, start condition function)  
Clock source................ 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency; NSBT1 pin input  
Serial 2 : 8-bit × 1 (I²C)  
(master transmission/reception, slave transmission/reception)  
Clock source................ 1/144 to 1/252 of system clock; SCK pin input  
MAD00033EEM  

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