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MMC2075VF001 PDF预览

MMC2075VF001

更新时间: 2024-11-20 22:16:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器
页数 文件大小 规格书
34页 760K
描述
Integrated Processor with Roaming FLEX Decoder

MMC2075VF001 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA, BGA144,13X13,32
针数:144Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.88
具有ADC:NO地址总线宽度:22
位大小:32最大时钟频率:10 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:16JESD-30 代码:S-PBGA-B144
JESD-609代码:e0长度:12 mm
I/O 线路数量:22端子数量:144
最高工作温度:85 °C最低工作温度:-20 °C
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA144,13X13,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3 V
认证状态:Not QualifiedRAM(字节):6144
ROM(单词):24576ROM可编程性:MROM
座面最大高度:1.6 mm速度:10 MHz
子类别:Microcontrollers最大供电电压:3.6 V
最小供电电压:1.8 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:12 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

MMC2075VF001 数据手册

 浏览型号MMC2075VF001的Datasheet PDF文件第2页浏览型号MMC2075VF001的Datasheet PDF文件第3页浏览型号MMC2075VF001的Datasheet PDF文件第4页浏览型号MMC2075VF001的Datasheet PDF文件第5页浏览型号MMC2075VF001的Datasheet PDF文件第6页浏览型号MMC2075VF001的Datasheet PDF文件第7页 
MMC2080/2075/D  
Rev. 0, 10/1999  
Semiconductor Products Sector  
MMC2080/2075  
Advance Information  
MMC2080/2075 Integrated Processor with  
Roaming FLEX™ Decoder  
Part 1 Introduction  
The MMC2080/2075 is designed to provide the messaging and paging marketplace with a powerful and  
flexible solution to carry communications design into the next millennium. The MMC2080 integrates two  
of Motorola’s most successful product families, M•CORE™ and the Roaming FLEX™ alphanumeric  
decoders, a combination that will set a new standard in the communications industry. Except for the FLEX  
decoder, the MMC2075 offers all features of the MMC2080.  
Both the The MMC2080/2075 are members of the low-power, high-performance M•CORE family of 32-bit  
microcontroller units (MCUs). The M•CORE is a streamlined execution engine that provides many of the  
performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining  
performance, speed, and cost efficiency in a compact, low-power design, the M•CORE microRISC  
architecture is a natural solution for applications where battery life and systems cost are critical design goals.  
Given that a total system’s components and processor core determine its power consumption, the instruction  
set architecture (ISA) for the M•CORE is designed to optimize the trade-off between performance and total  
power consumption. The result is system-wide reduction of total energy consumption with maintenance of  
acceptable performance levels. Memory power consumption (both on-chip and external) is a major factor in  
system energy consumption. By adopting 16-bit instruction encoding, and thus significantly decreasing the  
memory bandwidth needed for a high rate of instruction execution, the MMC2080/2075 minimizes the  
overhead of memory system energy consumption.  
The MMC2080/2075 also reduces power consumption by coupling a fully static design with dynamic power  
management and low-voltage operation. Versatile power management is achieved through automatic power  
downs of any internal functional blocks not needed on a clock-by-clock basis. Power conservation modes  
are also provided for absolute power conservation.  
A table of contents for this document appears on the following page. Figure 1 on page 3 and Figure 2 on  
page 4 provide simplified block diagrams of the MMC2080/2075.  
This document contains information on a new product. Specifications and information herein  
are subject to change without notice.  
© Motorola, Inc., 1999. All rights reserved.  
 

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