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MM74HCT573 PDF预览

MM74HCT573

更新时间: 2024-02-05 09:31:57
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器
页数 文件大小 规格书
6页 130K
描述
TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop

MM74HCT573 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.09
Is Samacsys:N其他特性:BROADSIDE VERSION OF 373
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8015 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.0072 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:38 ns传播延迟(tpd):44 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

MM74HCT573 数据手册

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PRELIMINARY  
February 1990  
MM54HCT573/MM74HCT573  
TRI-STATE Octal D-Type Latch  
É
MM54HCT574/MM74HCT574  
TRI-STATE Octal D-Type Flip-Flop  
General Description  
The MM54HCT573/MM74HCT573 octal D-type latches and  
MM54HCT574/MM74HCT574 Octal D-type flip flops ad-  
vanced silicon-gate CMOS technology, which provides the  
inherent benefits of low power consumption and wide power  
supply range, but are LS-TTL input and output characteristic  
& pin-out compatible. The TRI-STATE outputs are capable  
of driving 15 LS-TTL loads. All inputs are protected from  
positive going transitions of the CLOCK (CK) input. When a  
high logic level is applied to the OUTPUT CONTROL (OC)  
input, all outputs go to a high impedance state, regardless  
of what signals are present at the other inputs and the state  
of the storage elements.  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
devices. These parts are also plug in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
damage due to static discharge by internal diodes to V  
and ground.  
CC  
When the MM54HCT573/MM74HCT573 LATCH ENABLE  
input is high, the Q outputs will follow the D inputs. When  
the LATCH ENABLE goes low, data at the D inputs will be  
retained at the outputs until LATCH ENABLE returns high  
again. When a high logic level is applied to the OUTPUT  
CONTROL input, all outputs go to a high impedance state,  
regardless of what signals are present at the other inputs  
and the state of the storage elements.  
Features  
Y
TTL input characteristic compatible  
Y
Typical propagation delay: 18 ns  
Y
Low input current: 1 mA maximum  
Y
Low quiescent current: 80 mA maximum  
Y
Compatible with bus-oriented systems  
The MM54HCT574/MM74HCT574 are positive edge trig-  
gered flip-flops. Data at the D inputs, meeting the setup and  
hold time requirements, are transferred to the Q outputs on  
Y
Output drive capability: 15 LS-TTL loads  
Connection Diagram  
Dual-In-Line Package  
TL/F/10627–1  
TL/F/10627–2  
Top View  
Order Number MM54HCT573* or MM74HCT573*  
Top View  
Order Number MM54HCT574* or MM74HCT574*  
*Please look into Section 8, Appendix D for availability of various package types.  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10627  
RRD-B30M105/Printed in U. S. A.  

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