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MM74HCT573J PDF预览

MM74HCT573J

更新时间: 2024-01-28 22:49:02
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器
页数 文件大小 规格书
6页 130K
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MM74HCT573J 数据手册

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PRELIMINARY  
February 1990  
MM54HCT573/MM74HCT573  
TRI-STATE Octal D-Type Latch  
É
MM54HCT574/MM74HCT574  
TRI-STATE Octal D-Type Flip-Flop  
General Description  
The MM54HCT573/MM74HCT573 octal D-type latches and  
MM54HCT574/MM74HCT574 Octal D-type flip flops ad-  
vanced silicon-gate CMOS technology, which provides the  
inherent benefits of low power consumption and wide power  
supply range, but are LS-TTL input and output characteristic  
& pin-out compatible. The TRI-STATE outputs are capable  
of driving 15 LS-TTL loads. All inputs are protected from  
positive going transitions of the CLOCK (CK) input. When a  
high logic level is applied to the OUTPUT CONTROL (OC)  
input, all outputs go to a high impedance state, regardless  
of what signals are present at the other inputs and the state  
of the storage elements.  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
devices. These parts are also plug in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
damage due to static discharge by internal diodes to V  
and ground.  
CC  
When the MM54HCT573/MM74HCT573 LATCH ENABLE  
input is high, the Q outputs will follow the D inputs. When  
the LATCH ENABLE goes low, data at the D inputs will be  
retained at the outputs until LATCH ENABLE returns high  
again. When a high logic level is applied to the OUTPUT  
CONTROL input, all outputs go to a high impedance state,  
regardless of what signals are present at the other inputs  
and the state of the storage elements.  
Features  
Y
TTL input characteristic compatible  
Y
Typical propagation delay: 18 ns  
Y
Low input current: 1 mA maximum  
Y
Low quiescent current: 80 mA maximum  
Y
Compatible with bus-oriented systems  
The MM54HCT574/MM74HCT574 are positive edge trig-  
gered flip-flops. Data at the D inputs, meeting the setup and  
hold time requirements, are transferred to the Q outputs on  
Y
Output drive capability: 15 LS-TTL loads  
Connection Diagram  
Dual-In-Line Package  
TL/F/10627–1  
TL/F/10627–2  
Top View  
Order Number MM54HCT573* or MM74HCT573*  
Top View  
Order Number MM54HCT574* or MM74HCT574*  
*Please look into Section 8, Appendix D for availability of various package types.  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10627  
RRD-B30M105/Printed in U. S. A.  

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