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MM74HCT164N PDF预览

MM74HCT164N

更新时间： 2024-11-27 21:20:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
4页 121K
描述
HCT SERIES, 1-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP14, PLASTIC, DIP-14

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MM74HCT164N 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：DIP, DIP14,.3Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.71
Is Samacsys：N计数方向：RIGHT
系列：HCTJESD-30 代码：R-PDIP-T14
JESD-609代码：e0长度：19.18 mm
负载电容（CL）：50 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：25000000 Hz位数：1
功能数量：8端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V传播延迟（tpd）：38 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Shift Registers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：25 MHz
Base Number Matches：1

MM74HCT164N 数据手册

 浏览型号MM74HCT164N的Datasheet PDF文件第2页浏览型号MM74HCT164N的Datasheet PDF文件第3页浏览型号MM74HCT164N的Datasheet PDF文件第4页 
January 1988  
MM54HCT164/MM74HCT164  
8-Bit Serial-in/Parallel-out Shift Register  
General Description  
The MM54HCT164/MM74HCT164 utilizes advanced sili-  
con-gate CMOS technology. It has the high noise immunity  
and low consumption of standard CMOS integrated circuits.  
It also offers speeds comparable to low power Schottky de-  
vices.  
The 54HCT/74HCT logic family is functionally as well as  
pin-out compatible with the standard 54LS/74LS logic fami-  
ly. All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
devices. These parts are also plug-in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
This 8-bit shift register has gated serial inputs and CLEAR.  
Each register bit is a D-type master/slave flip flop. Inputs A  
& B permit complete control over the incoming data. A low  
at either or both inputs inhibits entry of new data and resets  
the first flip flop to the low level at the next clock pulse. A  
high level on one input enables the other input which will  
then determine the state of the first flip flop. Data at the  
serial inputs may be changed while the clock is high or low,  
but only information meeting the setup and hold time re-  
quirements will be entered. Data is serially shifted in and out  
of the 8-bit register during the positive going transition of the  
clock pulse. Clear is independent of the clock and accom-  
plished by a low level at the CLEAR input.  
Features  
Y
Typical propagation delay: 20 ns  
Y
Low quiescent current: 40 mA maximum (74HCT Series)  
Y
Low input current: 1 mA maximum  
Y
Fanout of 10 LS-TTL loads  
Y
TTL input compatible  
Connection Diagram  
Truth Table  
Dual-In-Line Package  
Inputs  
Clock  
Outputs  
. . .  
Clear  
A
B
Q
A
Q
Q
H
B
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
L
L
L
Q
AO  
Q
Q
HO  
BO  
H
L
L
Q
An  
Q
An  
Q
An  
Q
Q
Q
u
u
u
Gn  
Gn  
Gn  
X
e
e
e
Low Level (steady state)  
H
X
High Level (steady state), L  
Irrelevant (any input, including transitions)  
e
Transition from low to high level.  
u
e
the level of Q , Q , or Q , respectively, before the  
A B H  
Q
, Q , Q  
BO  
AO  
HO  
indicated steady state input conditions were established.  
e
the clock; indicated a one-bit shift.  
Q
, Q  
The level of Q or Q before the most recent  
A
transition of  
u
An  
Gn  
G
TL/F/5765–1  
Top View  
Order Number MM54HCT164 or MM74HCT164  
Logic Diagram  
TL/F/5765–2  
C
1995 National Semiconductor Corporation  
TL/F/5765  
RRD-B30M105/Printed in U. S. A.  
1234

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