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MM74HC245A PDF预览

MM74HC245A

更新时间: 2024-11-20 23:02:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 107K
描述
Octal 3-STATE Transceiver

MM74HC245A 数据手册

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September 1983  
Revised May 2005  
MM74HC245A  
Octal 3-STATE Transceiver  
General Description  
Features  
The MM74HC245A 3-STATE bidirectional buffer utilizes  
advanced silicon-gate CMOS technology, and is intended  
for two-way asynchronous communication between data  
buses. It has high drive current outputs which enable high  
speed operation even when driving large bus capaci-  
tances. This circuit possesses the low power consumption  
and high noise immunity usually associated with CMOS cir-  
cuitry, yet has speeds comparable to low power Schottky  
TTL circuits.  
Typical propagation delay: 13 ns  
Wide power supply range: 2–6V  
Low quiescent current: 80 A maximum (74 HC)  
3-STATE outputs for connection to bus oriented systems  
High output drive: 6 mA (minimum)  
Same as the 645  
This device has an active LOW enable input G and a direc-  
tion control input, DIR. When DIR is HIGH, data flows from  
the A inputs to the B outputs. When DIR is LOW, data flows  
from the B inputs to the A outputs. The MM74HC245A  
transfers true data from one bus to the other.  
This device can drive up to 15 LS-TTL Loads, and does not  
have Schmitt trigger inputs. All inputs are protected from  
damage due to static discharge by diodes to VCC and  
ground.  
Ordering Code:  
Order Number  
MM74HC245AWM  
MM74HC245ASJ  
MM74HC245AMTC  
MM74HC245AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
M20D  
MTC20  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Control  
Inputs  
Operation  
G
L
DIR  
L
H
X
B data to A bus  
A data to B bus  
Isolation  
L
H
H
L
X
HIGH Level  
LOW Level  
Irrelevant  
Top View  
© 2005 Fairchild Semiconductor Corporation  
DS005165  
www.fairchildsemi.com  

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