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MM54C74J PDF预览

MM54C74J

更新时间: 2024-01-03 05:12:06
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 123K
描述
Dual D Flip-Flop

MM54C74J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-XDIP-T14
JESD-609代码:e0逻辑集成电路类型:D FLIP-FLOP
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5/15 V
认证状态:Not Qualified筛选级别:MIL-STD-883 Class B (Modified)
子类别:FF/Latches表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:POSITIVE EDGEBase Number Matches:1

MM54C74J 数据手册

 浏览型号MM54C74J的Datasheet PDF文件第2页浏览型号MM54C74J的Datasheet PDF文件第3页浏览型号MM54C74J的Datasheet PDF文件第4页浏览型号MM54C74J的Datasheet PDF文件第5页浏览型号MM54C74J的Datasheet PDF文件第6页 
February 1988  
MM54C74/MM74C74 Dual D Flip-Flop  
General Description  
Y
Low power  
50 nW (typ.)  
10 MHz (typ.)  
with 10V supply  
The MM54C74/MM74C74 dual D flip-flop is a monolithic  
complementary MOS (CMOS) integrated circuit constructed  
with N- and P-channel enhancement transistors. Each flip-  
flop has independent data, preset, clear and clock inputs  
and Q and Q outputs. The logic level present at the data  
input is transferred to the output during the positive going  
transition of the clock pulse. Preset or clear is independent  
of the clock and accomplished by a low level at the preset  
or clear input.  
Y
Medium speed operation  
Applications  
Y
Automotive  
Y
Data terminals  
Y
Instrumentation  
Y
Medical electronics  
Y
Alarm system  
Features  
Y
Y
Industrial electronics  
Supply voltage range  
3V to 15V  
2
Drive 2 LPT L loads  
Y
Remote metering  
Y
Y
Tenth power TTL compatible  
High noise immunity  
Y
Computers  
0.45 V  
CC  
(typ.)  
Logic Diagram  
TL/F/5885–1  
Truth Table  
Connection Diagram  
Dual-In-Line Package  
Preset  
Clear  
Q
n
Q
n
0
0
1
1
0
1
0
1
0
0
1
0
0
1
*Q  
*Q  
n
n
*No change in output from previous state.  
Order Number MM54C74 or MM74C74  
TL/F/5885–2  
Top View  
Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’.  
A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’.  
C
1995 National Semiconductor Corporation  
TL/F/5885  
RRD-B30M105/Printed in U. S. A.  

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