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MM54C373W PDF预览

MM54C373W

更新时间: 2024-02-01 04:49:36
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器
页数 文件大小 规格书
8页 172K
描述
IC,LATCH,SINGLE,8-BIT,CMOS,FP,20PIN,CERAMIC

MM54C373W 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.79
逻辑集成电路类型:BUS DRIVERBase Number Matches:1

MM54C373W 数据手册

 浏览型号MM54C373W的Datasheet PDF文件第2页浏览型号MM54C373W的Datasheet PDF文件第3页浏览型号MM54C373W的Datasheet PDF文件第4页浏览型号MM54C373W的Datasheet PDF文件第5页浏览型号MM54C373W的Datasheet PDF文件第6页浏览型号MM54C373W的Datasheet PDF文件第7页 
March 1988  
MM54C373/MM74C373 TRI-STATE Octal D-Type Latch  
É
MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop  
General Description  
The MM54C373/MM74C373, MM54C374/MM74C374 are  
integrated, complementary MOS (CMOS), 8-bit storage ele-  
ments with TRI-STATE outputs. These outputs have been  
specially designed to drive high capacitive loads, such as  
one might find when driving a bus, and to have a fan out of 1  
when driving standard TTL. When a high logic level is ap-  
plied to the OUTPUT DISABLE input, all outputs go to a high  
impedance state, regardless of what signals are present at  
the other inputs and the state of the storage elements.  
Both the MM54C373/MM74C373 and the MM54C374/  
MM74C374 are being assembled in 20-pin dual-in-line pack-  
ages with 0.300 pin centers.  
×
Features  
Y
Wide supply voltage range  
High noise immunity  
Low power consumption  
TTL compatibility  
3V to 15V  
0.45 V (typ.)  
Y
Y
Y
CC  
Fan out of 1  
driving standard TTL  
The MM54C373/MM74C373 is an 8-bit latch. When LATCH  
ENABLE is high, the Q outputs will follow the D inputs.  
When LATCH ENABLE goes low, data at the D inputs,  
which meets the set-up and hold time requirements, will be  
retained at the outputs until LATCH ENABLE returns high  
again.  
Y
Y
Y
Y
Bus driving capability  
TRI-STATE outputs  
Eight storage elements in one package  
Single CLOCK/LATCH ENABLE and OUTPUT  
DISABLE control inputs  
The MM54C374/MM74C374 is an 8-bit, D-type, positive-  
edge triggered flip-flop. Data at the D inputs, meeting the  
set-up and hold time requirements, is transferred to the Q  
outputs on positive-going transitions of the CLOCK input.  
Y
20-pin dual-in-line package with 0.300 centers takes  
×
half the board space of a 24-pin package  
Connection Diagrams  
MM54C373/MM74C373  
Dual-In-Line Package  
MM54C374/MM74C374  
Dual-In-Line Package  
TL/F/5906–1  
TL/F/5906–2  
Top View  
Top View  
Order Number MM54C373 or MM74C373  
Order Number MM54C374 or MM74C374  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/5906  
RRD-B30M105/Printed in U. S. A.  

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