Datasheet > MM24256-AMN5T

MM24256-AMN5T

更新时间： 2024-01-31 22:32:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
20页	125K
描述
256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines

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数据手册

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MM24256-AMN5T 数据手册

M24256-A

C Bus EEPROM

256 Kbit Serial

With Two Chip Enable Lines

PRELIMINARY DATA

■ Compatible with I C Extended Addressing

■ Two Wire I C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24256-A

TSSOP14 (DL)

169 mil width

– 2.5V to 5.5V for M24256-AW

– 1.8V to 3.6V for M24256-AR

■ 2 Chip Enable Inputs: up to four memories can

PSDIP8 (BN)

0.25 mm frame

SBGA

be connected to the same I C bus

■ Hardware Write Control

SBGA7 (EA)

140 x 90 mil

■ BYTE and PAGE WRITE (up to 64 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Timed Programming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 100,000 Erase/Write Cycles

■ More than 40 Year Data Retention

SO8 (MN)

150 mil width

SO8 (MW)

200 mil width

DESCRIPTION

These I C-compatible electrically erasable pro-

grammable memory (EEPROM) devices are orga-

nized as 32Kx8 bits, and operate down to 2.5 V

(for the M24256-AW), and down to 1.8 V (for the

M24256-AR).

Figure 1. Logic Diagram

The M24256-A is available in Plastic Dual-in-Line,

Plastic Small Outline and Thin Shrink Small Out-

line packages. The M24256-A is also available in

a chip-scale (SBGA) package.

E0-E1

SCL

SDA

Table 1. Signal Names

M24256-A

E0, E1

SDA

SCL

Chip Enable

Serial Data

Serial Clock

Write Control

Supply Voltage

Ground

AI02271C

April 2000

1/20

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

12 3 4 5 6 7...20

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