MLX90251
Programmable Linear Hall Effect Sensor
Features and Benefits
Application Examples
ꢀ Analog Signal Processing
ꢀ Quad Switched Hall Plate
ꢀ Chopper Stabilized Amplifier
ꢀ Linear Analog Ratiometric Output Voltage
ꢀ Programmable Output Quiescent Voltage (VOQ
-100%VDD…200%VDD Range
ꢀ Linear Position Sensing
ꢀ Rotary Position Sensing
ꢀ Current Sensing
ꢀ
Magnetic Field Measurement
)
ꢀ Programmable Magnetic Sensitivity
ꢀ Programmable Low Pass Filter
ꢀ Programmable Clamping Voltage
ꢀ Programmable Temperature Compensation
ꢀ Melexis ID Number
ꢀ Programmable Customer ID Number
ꢀ Lead-free package
Ordering Information
Part No.
MLX90251
Temperature Code
E (-40°C to 85°C)
L (-40°C to 150°C)
E (-40°C to 85°C)
Package† Code
VA (4 Lead SIP)
Option Code††
0, 1, 2, 3
MLX90251
GO (TSSOP14)
0, 1, 2, 3
Example:
MLX90251LVA-2
MLX90251EGO-2
† Both package types (VA and GO) are lead-free (see section 15).
†† Please see section 10.4 for detailed information on the option code.
1 Functional Diagram
2 General Description
The MLX90251 is
a
CMOS Programmable,
1
Supply
Ratiometric Linear Hall Effect sensor IC. The
linear output voltage is proportional to the
magnetic flux density. The ratiometric output
voltage is proportional to the supply voltage. The
MLX90251 possesses active error correction
circuitry, which virtually eliminates the offset errors
normally associated with analog Hall Effect
devices. All the parameters of the MLX90251
transfer characteristic are fully programmable.
The VOQ (VOUT @ B = 0 Gauss), the Sensitivity,
the slope polarity, the Output Clamping levels, the
thermal Sensitivity drift, the internal bias point and
a low-pass filter are all programmable in end-user
applications. The MLX90251 has a very stable
thermal compensation for both the Sensitivity and
the VOQ over a broad temperature range. For
traceability purpose the MLX90251 will carry a
unique ID number programmed by Melexis and 24
bits of EEPROM memory are allocated for a user
programmed serial number.
OPA
Filter
OPA
OPA
4
2
3
Program
decoder
Shift Register
E E P R O M
Figure 1-1 Functional Diagram
Pin Out
VA
1
2
3
4
GO
2
3
VDD
Test
VSS (Ground)
VOUT
NC
5
6
1, 4, 7, 8-14
Table 1: Pin out
3901090251
Rev 009
Page 1 of 22
Data Sheet
Nov/06