Datasheet > ML87V5002

ML87V5002

更新时间： 2024-02-26 11:36:54

品牌	Logo	应用领域
冲电气 - OKI		光电二极管商用集成电路
页数	文件大小	规格书
36页	309K
描述
Consumer Circuit, PDSO32, TSOP1-32

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ML87V5002 技术参数

生命周期：	Transferred	零件包装代码：	TSOP1
包装说明：	TSOP1,	针数：	32
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.39	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G32	长度：	12.4 mm
功能数量：	1	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP1
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	宽度：	8 mm
Base Number Matches：	1

ML87V5002 数据手册

FEDL87V5002-01

OKI Semiconductor

Issue Date: Sep. 1, 2005

ML87V5002

Audio Delay IC with Built-in 2-Mbit DRAM

GENERAL DESCRIPTION

The ML87V5002 has been developed for solving “Lip-sync problems” in DVD systems, hard disc recording

devices, digital TVs and Home Theater Systems. The ML87V5002 can delay the digital audio signal of each of

eight channels by setting each register. The ML87V5002 is suitable for synchronizing sounds with motions when

loads are too heavy for DSP to control audio delay.

The ML87V5002 does not require any external memory for the audio delay because the ML87V5002 has a built-in

2-Mbit DRAM. The maximum delay time is, for example, 341.3 ms at 48 kHz in 8-ch mode and 1.365 sec at 48

kHz in 2-ch mode. Supporting two to eight audio channels; the ML87V5002 is suitable for applications ranging

from simple stereo systems to multi-channel systems. The granularity of the delay time is the sampling period, or

Ts. The delay time of each channel can be set in steps of Ts.

The ML87V5002 interfaces to most audio LSIs since the ML87V5002 supports general digital audio formats, such

as I²S, right justified, and left justified. In addition, suitable digital audio formats can be selected as each of the

input and output formats.

FEATURES

• Digital audio delay control: The digital audio signals input from the DI0-DI3 pins are delayed for specific

delay times set by an external device and are output from the DO0-DO3 pins.

• No external memory: No external memory is required for the delay because the 2-Mbit DRAM is included.

• Three digital-audio formats: I²S, right justified and left justified formats.

• Input/output format settings: I²S, right justified, or left justified format can be selected as each of the input

and output formats.

• Data bit lengths: 16/20/24/32 bits

• Wide range sampling frequencies: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz

• Maximum audio delay time:

The maximum delay time (when the audio data length is 16 bits)

- 1.365 sec (48 kHz, 2-ch mode)

- 682.5 ms (96 kHz, 2-ch mode)

- 341.3 ms (192 kHz, 2-ch mode)

- 341.3 ms (48 kHz, 8-ch mode)

- 170.7 ms (96 kHz, 8-ch mode)

- 85.3 ms

(192 kHz, 8-ch mode)

• Standard host interface: I²C slave interface is supported.

• Minimum delay time step: The granularity of delay time is Ts.

• Independent delay time setting: The delay time of each channel can be set.

• General power supply voltage: 3.3 V ±0.3V

• 5V tolerant I/O: Audio interface inputs, I²C, and INT are tolerant to 5 V.

• Package:

32-pin plastic TSOP type I (TSOP(1)32-P-0814-0.50-1K)

Note:

• System clock requirements

- Frequency

The frequency of the system clock should be 128 times the sampling frequency or more. When the

sampling frequency is 192 kHz, be sure to set the system clock frequency at 128 times the sampling

frequency.

- Phase

The system clock should be synchronized with LRCK and the BCK. In synchronized condition, the phase

variation is acceptable.

1/36

12 3 4 5 6 7...36

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