FEDL5243_001-04
ML5243
■ Pin Description
Pin No. Pin name I/O
Description
Power supply input pin.
Connect an external CR filter for noise rejection.
1
VDD
—
Battery cell 5 high voltage input pin.
2
3
4
5
6
7
V5
V4
I
I
I
I
I
I
Battery cell 5 low voltage input and Battery cell 4 high voltage input pin.
Battery cell 4 low voltage input and Battery cell 3 high voltage input pin.
Battery cell 3 low voltage input and Battery cell 2 high voltage input pin.
Battery cell 2 low voltage input and Battery cell 1 high voltage input pin.
Ground pin.
V3
V2
V1
GND
Current sense resistor input pin. Connect a resistor of the resistance value corresponding
to the detecting current between this pin and the GND pin. Should be tied to GND if not
used.
8
9
ISENSE
N.C.
I
No connected. Connect to GND or Leave it electrically unconnected.
Discharge enable pin.
Output type is selected from CMOS / NMOS open drain / PMOS open drain. And its
asserted level is selected from “L” level/”H” level.
10
DCHG
O
Charge enable pin.
Output type is selected from CMOS / NMOS open drain / PMOS open drain. And its
asserted level is selected from “L” level/”H” level.
11
12
CHG
O
Load/charger connection detecting input pin. Load or charger presence is decided by this
input level.
VRSNS
IO
2nd overvoltage alarm output. Output type is selected from CMOS / NMOS open drain /
PMOS open drain. And its asserted level is selected from “L” level/”H” level.
13
14
PF
O
Ground pin.
GND
—
Detection delay time reduced test input pin.
Every detection delay time is reduced by setting the voltage of this pin as VREG pin level.
Internal 10k pull-down resistor is connected.
15
TEST
I
Input pin for high/low temperature charge/discharge inhibition detection. Connect a
thermistor between this pin and GND. Should be tied to the VNTC pin through 10k
resistor if not used.
Thermistor power supply. Should be connected to TSNS through a 4.7 k resistor.
If not used, this 4.7 k resistor should be connected.
16
17
TSNS
VNTC
I
O
Pins to specify battery cell number. Either the VREG or the GND level should be applied.
CS1
CS0
Number of connected
Battery cells
5 cell
18,19 CS0,CS1 IO
GND
GND
GND
VREG
4 cell
VREG
GND / VREG
3 cell
Built-in 3.3 V regulator output pin. Should be tied to GND through a 1 F or larger
capacitor. Do not use this pin as power supply for an external circuit.
20
VREG
O
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