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MK74CG117BFT PDF预览

MK74CG117BFT

更新时间: 2024-02-01 23:25:01
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 158K
描述
Clock Generator, 100MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48

MK74CG117BFT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:0.300 INCH, SSOP-48针数:48
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.2
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:100 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
主时钟/晶体标称频率:55 MHz认证状态:Not Qualified
座面最大高度:2.8 mm子类别:Clock Generators
最大供电电压:3.63 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MK74CG117BFT 数据手册

 浏览型号MK74CG117BFT的Datasheet PDF文件第2页浏览型号MK74CG117BFT的Datasheet PDF文件第3页浏览型号MK74CG117BFT的Datasheet PDF文件第4页浏览型号MK74CG117BFT的Datasheet PDF文件第5页浏览型号MK74CG117BFT的Datasheet PDF文件第6页浏览型号MK74CG117BFT的Datasheet PDF文件第7页 
MK74CG117B  
16 Output Low Skew Clock Generator  
Description  
Features  
The MK74CG117B is a monolithic CMOS high speed,  
low-skew clock driver that includes an on-chip PLL.  
Ideal for communications and other systems that  
require a large number of high-speed clocks, the  
unique combination of PLL and 16 low-skew outputs  
can eliminate oscillators and low skew buffers from  
systems.  
48-pin SSOP (300 mil) package  
On-chip PLL generates output clocks up to 100 MHz  
from a simple crystal or clock input  
16 low-skew outputs  
Output skew less than 250 ps on rising edges  
Ability to configure as  
–16 clocks at full frequency  
The device has a number of built in multipliers, making  
it possible to run from one inexpensive, low frequency  
crystal, and produce high frequency clock outputs.  
Another selection allows the chip to run as a divider,  
dividing the input clock by two (or 4 using the mode  
select).  
–12 at full and 4 at half frequency  
–8 at full and 8 at half frequency  
Tri-state mode for Output Enable function  
3.3 V 5ꢀ supply voltage  
Industrial temperature version available  
The device also has a buffered reference output,  
allowing multiple devices to be easily driven from one  
clock source.  
Block Diagram  
VDD  
9
3
Clock 1  
Clock  
S2:0  
2
Synthesis  
and Mode  
Select  
Clock 2  
M1:0  
Circuitry  
Clock 16  
REF  
X1/ICLK  
Crystal or  
clock input  
Crystal  
Ocsillator  
X2  
10  
The crystal requires external capacitors for  
accurate tuning of the clock  
GND  
MDS 74CG117B A  
1
Revision 041604  
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com  

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