Datasheet > MK74CG117FLFT

MK74CG117FLFT

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
5页	69K
描述
Clock Generator, 100MHz, CMOS, PDSO48, SSOP-48

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MK74CG117FLFT 数据手册

MK74CG117

16 Output Low Skew Clock Generator

Description

Features

The MK74CG117 is a monolithic CMOS high speed,

low-skew clock driver that includes an on-chip PLL.

Ideal for communications and other systems that

require a large number of high-speed clocks, the

unique combination of PLL and 16 low-skew outputs

can eliminate oscillators and low skew buffers from

systems.

• 48 pin SSOP (300 mil) package

• On-chip PLL generates output clocks up to

100 MHz from a simple crystal or clock input

• 16 low skew outputs

• Output skew less than 250 ps on rising edges

• Ability to configure as

The device has a number of built in multipliers, making

it possible to run from one inexpensive, low frequency

crystal, and produce high frequency clock outputs.

Another selection allows the chip to run as a divider,

dividing the input clock by two (or 4 using the mode

select).

- 16 clocks at full frequency

- 12 at full and 4 at half frequency

- 8 at full and 8 at half frequency

• Tri-state mode for Output Enable function

• 3.3 V±5% supply voltage

• Industrial temperature version available

The device also has a buffered reference output,

allowing multiple devices to be easily driven from one

clock source.

VDD

GND

Block Diagram

S2:0

M1:0

Output

Clock 1

Buffer

Clock

Synthesis

and Mode

Select

Output

Clock 2

Buffer

Circuitry

Crystal or clock

Output

Clock 16

Buffer

input

X1/ICLK

Crystal

Oscillator

Output

REF

Buffer

MDS 74CG117 D

Revision 041502

Integrated Circuit Systems • 525 Race Street. • San Jose • CA•95126 • (408)295-9800tel • www.icst.com

12 3 4 5

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