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MK28FN2M0VMI15 PDF预览

MK28FN2M0VMI15

更新时间: 2024-11-22 01:21:55
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
87页 1058K
描述
Kinetis K28F MCU Sub-Family

MK28FN2M0VMI15 数据手册

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NXP Semiconductors  
Data Sheet: Technical Data  
K28P210M150SF5  
Rev. 4, 03/2017  
Kinetis K28F MCU Sub-Family  
MK28FN2M0CAU15R  
MK28FN2M0VMI15  
High performance ARM® Cortex®-M4 MCU with 2 MB Flash,  
1 MB SRAM, 2 USB Controllers (High-Speed and Full-  
Speed), SDRAM controller, QuadSPI interface and Power  
Management Controller with Core Voltage Bypass.  
K28F extends the Kinetis Micontroller portfolio with large  
embedded memory, advanced external memory interfaces,  
performance, and peripheral integration while maintaining a high  
level of software compatibility with previous Kinetis devices:  
• The extended memory resources include a total of 2 MB of  
programmable flash and 1 MB of embedded SRAM which  
can be used to support application needs for data logging  
and rich human to machine interfaces with displays  
• The Power Management Controller with Core Voltage  
Bypass enables the use of an external PMIC to maximize  
the power efficiency of the system  
169 MAPBGA (MI)  
9 x 9 x 1.28 mm Pitch 6.9 mm x 6.9 x 0.6 mm  
0.65 mm Pitch 0.4 mm  
210 WLCSP (AU)  
• K28F enables memory expansion leveraging the SDRAM  
controller and QuadSPI interface for eXecution-In-Place (XIP) from an external Serial NOR flash  
• Both the USB High-Speed and Crystal-less Full-Speed Controllers integrate a PHY to reduce BOM cost  
• The integrated smart peripherals such as Low-power UARTs and Timers operate in very low-power  
modes to optimize battery life of the system  
Performance  
• Up to 150 MHz ARM Cortex-M4 based core with DSP  
Human-machine interface  
• Up to 120 General-purpose input/output (GPIOs)  
instructions and Single Precision Floating Point unit  
(FPU)  
Analog modules  
• Power Management Control (PMC) with Core Voltage  
Bypass  
• One 16-bit SAR ADCs, two 6-bit DAC and one 12-bit  
DAC  
Memories and memory expansion  
• 2 MB dual bank program flash and 1 MB SRAM  
• 8 KB I/D + 8 KB System cache  
• 32-bit external bus interface (FlexBus)  
• 32-bit SDRAM controller  
• Dual QuadSPI interface with eXecution-In-Place (XIP)  
• supports SDR and DDR serial flash and octal  
configurations  
• Two analog comparators (CMP) containing a 6-bit  
DAC and programmable reference input  
• 1.2 V Voltage reference  
Timers  
• One 4-ch 32-bit Periodic interrupt timer  
• Two 16-bit low-power timer PWM modules  
• Two 8-ch motor control/general purpose/PWM timers  
• Two 2-ch quadrature decoder/general purpose timers  
• Real-time clock with independent 3.6 V power domain  
• Programmable delay block  
• 32 KB Boot ROM with built-in bootloader  
System and Clocks  
• 32-ch Asynchronous DMA  
• Multiple low-power modes  
• Memory protection unit with multi-master protection  
• 3 to 32 MHz main crystal oscillator  
• 32 kHz low power crystal oscillator  
• 48 MHz internal reference  
Operating Characteristics  
• Temperature range (ambient): -40 to 105°C (BGA)  
Temperature range (ambient):-40 to 85°C (WLCSP)  
• Hardware and Software Watchdogs  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  

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