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MK20N512VML100 PDF预览

MK20N512VML100

更新时间: 2024-09-24 10:55:07
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描述
K20 Sub-Family Data Sheet

MK20N512VML100 数据手册

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Document Number: K20P104M100SF2  
Rev. 1, 11/2010  
Freescale Semiconductor  
Data Sheet: Product Preview  
K20P104M100SF2  
K20 Sub-Family Data Sheet  
Supports the following:  
MK20N512VLL100, MK20N512VML100  
Features  
Human-machine interface  
– Low-power hardware touch sensor interface (TSI)  
– General-purpose input/output  
Operating Characteristics  
– Voltage range: 1.71 to 3.6 V  
– Flash write voltage range: 1.71 to 3.6 V  
– Temperature range (ambient): -40 to 105°C  
Analog modules  
– 16-bit SAR ADC with GA (x6
– 12-bit DAC  
– Analog comparat(CMcontaining a 6-bit DAC  
and programmble rence input  
– Voltage reference  
Performance  
– Up to 100 MHz ARM Cortex-M4 core with DSP  
instructions delivering 1.25 Dhrystone MIPS per  
MHz  
Memories and memory interfaces  
– Up to 512 KB program flash memory on non-  
FlexMemory devices  
Timers  
– Programable delay block  
– Eit-chael motor control/general purpose/PWM  
timers  
– Up to 128 KB RAM  
– Serial programming interface (EzPort)  
– FlexBus external bus interface  
– To-channel quadrature decoder/general purpose  
timers  
– Periodic interrupt timers  
– 16-bit low-power timer  
– Carrier modulator transmitter  
– Real-time clock  
Clocks  
– 1 to 32 MHz crystal oscillator  
– 32 kHz crystal oscillator  
– Multi-purpose clock generator  
Communication interfaces  
– USB full-/low-speed On-the-Go controller with on-  
chip transceiver  
– Controller Area Network (CAN) module  
– SPI modules  
– I2C modules  
– UART modules  
– Secure Digital host controller (SDHC)  
– I2S  
System peripherals  
– 10 low-power modes to provide pooptimization  
based on application requi
– Memory protection unit i-master  
protection  
– 16-channel DMA controller, pporting up to 64  
request sources  
– External watchdog monitor  
– Software watchdog  
– Low-leakage wakeup unit  
Security and integrity modules  
– Hardware CRC module to support fast cyclic  
redundancy checks  
– Hardware random-number generator  
– 128-bit unique identification (ID) number per chip  
This document contains information on a product under development. Freescale  
reserves the right to change or discontinue this product without notice.  
© 2010–2010 Freescale Semiconductor, Inc.  
Preliminary  

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