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MK1443-01STR PDF预览

MK1443-01STR

更新时间: 2024-12-01 15:43:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
4页 63K
描述
Processor Specific Clock Generator, 100MHz, CMOS, PDSO16, 0.150 INCH, SKINNY, SOIC-16

MK1443-01STR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.51
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:100 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:1.778 mm子类别:Clock Generators
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

MK1443-01STR 数据手册

 浏览型号MK1443-01STR的Datasheet PDF文件第2页浏览型号MK1443-01STR的Datasheet PDF文件第3页浏览型号MK1443-01STR的Datasheet PDF文件第4页 
MK1442/MK1443  
SCSI and Ethernet Clock Source  
Features  
Description  
The MK1442/3 are the ideal way to generate clocks for  
desktop computer motherboards and LAN  
workstations. Using analog Phase-Locked Loop (PLL)  
techniques, the devices accept a  
14.318 MHz crystal input to produce multiple output  
clocks up to 100 MHz. They provide 2XCPU, CPU,  
floppy controller, keyboard, system, SCSI and  
Ethernet clocks. The MK1442/3 are perfect for new  
Pentium™ Processor, PCI bus and 486 systems. The  
devices can operate at 5V or 3.3V up to and including  
80MHz on the CPU clock.  
• Provides exact frequency Ethernet and SCSI clocks  
• 5V or 3.3V (up to 80MHz) operation  
• Output clock frequencies up to 100 MHz  
• Pentium™ Processor compatible timing  
• 486 compatible smooth frequency transitions  
• Seven or eight output clocks  
• Compatible with X86 and 680X0 CPUs  
• Skew controlled 2X and 1X CPU to within 250ps  
• Packaged in 16 pin skinny SOIC or PDIP  
• Duty cycle of 47.5/52.5 up to 66.66 MHz  
• Duty cycle of 45/55 up to 100 MHz  
• Total of 15 different selectable CPU frequencies  
• Tri-state outputs for board level testing  
• 25mA drive capability at TTL levels  
• Keyboard frequencies of 12MHz (-01),  
8MHz (-02), or 16MHz (-03)  
The devices are identical except the MK1442 has an  
Output Enable (OE) pin that tri-states all outputs when  
taken low, and the MK1443 has an extra 14.318 MHz  
clock.  
• Advanced, low power CMOS process  
• MK1442 - output enable  
• MK1443 - two 14.318 MHz outputs  
Block Diagram  
VDD  
GND  
Output  
2XCPU  
CPUS0  
CPUS1  
Buffer  
Output  
÷2  
CPU  
Buffer  
8.00, 12.00,  
or 16.00 MHz  
Output  
Buffer  
Clock Synthesis  
and Control Circuitry  
Output  
Buffer  
24.00 MHz  
40.000 MHz  
20.000 MHz  
Output  
Buffer  
14.318 MHz  
crystal  
Output  
Buffer  
X1  
Output  
Buffer  
14.318 MHz  
(MK1443 only)  
Crystal  
Oscillator  
Output  
Buffer  
14.318 MHz  
X2  
OE (all outputs, MK1442 only)  
MDS 1442/3 F  
1
Revision 101001  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 •(408)297-1201tel • www.icst.com  

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