Datasheet > MIMXRT685SFAWB

MIMXRT685SFAWB

更新时间： 2025-08-21 15:19:03

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
171页	5605K
描述
i.MX RT600 Crossover MCU with Arm® Cortex®-M33 and DSP Cores

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MIMXRT685SFAWB 数据手册

RT600

Dual-core microcontroller with 32-bit Cortex^®-M33 and Xtensa

HiFi4 Audio DSP CPUs; Up to 4.5 MB SRAM; FlexSPI with

cache and dynamic decryption; High-speed USB device/host

+ Phy; 12-bit 1 Msamples/s ADC; Analog Comparator; Audio

subsystems supporting up to 8 DMIC channels; SDIO/eMMC;

AES/SHA/Crypto M33 coprocessor; PUF key generation

Rev. 2.1 — 7 July 2023

Product data sheet

1. General description

The RT600 is a family of dual-core microcontrollers for embedded applications featuring

an Arm Cortex-M33 CPU combined with a Cadence Xtensa HiFi4 advanced Audio Digital

Signal Processor CPU. The Cortex-M33 includes two hardware coprocessors providing

enhanced performance for an array of complex algorithms. The family offers a rich set of

peripherals and very low power consumption.

The Arm Cortex-M33 is a next generation core based on the ARMv8-M architecture that

offers system enhancements, such as ARM TrustZone® security, single-cycle digital

signal processing, and a tightly-coupled coprocessor interface, combined with low power

consumption, enhanced debug features, and a high level of support block integration. The

ARM Cortex-M33 CPU employs a 3-stage instruction pipe and includes an internal

prefetch unit that supports speculative branching. A hardware floating-point processor is

integrated into the core. On the RT600, the Cortex-M33 is augmented with two hardware

coprocessors providing accelerated support for additional DSP algorithms and

cryptography.

The Cadence Xtensa HiFi 4 Audio DSP engine is a highly optimized audio processor

designed especially for efficient execution of audio and voice codecs and pre- and

post-processing modules. It supports four 32x32-bit MACs, some support for 72-bit

accumulators, limited ability to support eight 32x16-bit MACs, and the ability to issue two

64-bit loads per cycle. There is a floating point unit providing up to four single-precision

IEEE floating point MACs per cycle.

The RT600 provides up to 4.5 MB of on-chip SRAM (plus an additional 128 KB of

tightly-coupled HiFi4 ram) and several high-bandwidth interfaces to access off-chip flash.

The FlexSPI flash interface supports two channels and includes an 32 KB cache and an

on-the-fly decryption engine. The RT600 is designed to allow the Cortex-M33 to operate

at frequencies of up to 300 MHz and the HiFi4 DSP to operate at frequencies of up to 600

MHz.

1.1 Peripherals

The peripheral complement includes an FlexSPI flash interface with two channels, two

SDIO/eMMC interfaces, a high-speed USB device/host with on-chip PHY, a 12-bit, 1

MSamples/sec ADC with temperature sensor, an analog comparator, AES256 and Hash

engines with Physical Unclonable Function (PUF) key generation, a digital microphone

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