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MH16D64AKQJ-75 PDF预览

MH16D64AKQJ-75

更新时间: 2024-10-01 19:48:07
品牌 Logo 应用领域
三菱 - MITSUBISHI 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
41页 364K
描述
DDR DRAM Module, 16MX64, 0.75ns, CMOS, SODIMM-200

MH16D64AKQJ-75 技术参数

生命周期:Obsolete零件包装代码:MODULE
包装说明:DIMM, DIMM200,24针数:200
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.32风险等级:5.84
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.75 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N200
内存密度:1073741824 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:200
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM200,24
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:2.5 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
子类别:DRAMs最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.6 mm端子位置:DUAL
Base Number Matches:1

MH16D64AKQJ-75 数据手册

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Preliminary Spec.  
Some contents are subject to change without notice.  
MITSUBISHI LSIs  
MH16D64AKQJ-75,-10  
1,073,741,824-BIT (16,777,216-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module  
- Utilizes industry standard 16M X 16 DDR Synchronous DRAMs  
DESCRIPTION  
in TSOP package , industry standard EEPROM(SPD) in  
TSSOP package  
The MH16D64AKQJ is 16777216 - word x 64-bit Double  
Data Rate(DDR) Sy nchronous DRAM mounted module.  
This consists of 4 industry standard 16M x 16 DDR  
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which  
achiev es v ery high speed data rate up to 133MHz.  
This socket-ty pe memory module is suitable f or main  
memory in computer systems and easy to interchange or  
add modules.  
- 200pin SO-DIMM  
- Vdd=Vddq=2.5v ±0.2V  
- Double data rate architecture; two data transf ers per  
clock cycle  
- Bidirectional, data strobe (DQS) is transmitted/receiv ed  
with data  
- Dif f erential clock inputs (CLK and /CLK)  
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS  
- Commands entered on each positiv e CLK edge  
- Data and data mask ref erenced to both edges of DQS  
- 4bank operation concontrolled by BA0,BA1(Bank Address  
,discrete)  
Operating Frequencies  
- /CAS latency - 2.0/2.5 (programmable)  
- Burst length- 2/4/8 (programmable)  
- Burst Ty pe - sequential/interleav e(programmable)  
- Auto precharge / All bank precharge controlled by A10  
- 8192 ref resh cycles /64ms  
Clock Rate  
Speed Grade  
CL=2  
CL=2.5  
133MHz  
125MHz  
-75  
-10  
100MHz  
100MHz  
- Auto ref resh and Self ref resh  
- Row address A0-12 / Column address A0-8  
- SSTL_2 Interf ace  
- Module 1bank Conf igration  
APPLICATION  
Main memory unit for Note PC, Mobile etc.  
PCB Outline  
(Front)  
(Back)  
1
2
199  
200  
MIT-DS-0457-0.0  
MITSUBISHI  
ELECTRIC  
16.Apr.2002  
1

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