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MH16D72AKLB-75 PDF预览

MH16D72AKLB-75

更新时间: 2024-09-30 22:05:35
品牌 Logo 应用领域
三菱 - MITSUBISHI 动态存储器
页数 文件大小 规格书
39页 347K
描述
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MH16D72AKLB-75 数据手册

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Preliminary Spec.  
Some contents are subject to change without notice.  
MITSUBISHI LSIs  
MH16D72AKLB-10,75  
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module  
DESCRIPTION  
The MH16D72AKLB is 16777216 - word x 72-bit Double  
Data Rate(DDR) Sy nchronous DRAM mounted module.  
This consists of 9 industry standard 16M x 8 DDR  
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which  
achiev es v ery high speed data rate up to 133MHz.  
This socket-ty pe memory module is suitable f or main  
memory in computer systems and easy to interchange or  
add modules.  
93pin  
1pin  
FEATURES  
CLK  
Max.  
Access Time  
[component level]  
Type name  
Frequency  
+ 0.75ns  
MH16D72AKLB-75  
MH16D72AKLB-10  
133MHz  
100MHz  
+ 0.8ns  
144pin  
145pin  
- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs  
in TSOP package , industry standard Registered Buffer in  
TSSOP package , and industry standard PLL in TSSOP package.  
- Vdd=Vddq=2.5v ±0.2V  
52pin  
53pin  
- Double data rate architecture; two data transf ers per  
clock cycle  
- Bidirectional, data strobe (DQS) is transmitted/receiv ed  
with data  
- Dif f erential clock inputs (CK0 and /CK0)  
- data and data mask ref erenced to both edges of DQS  
- /CAS latency - 2.0/2.5 (programmable)  
- Burst length- 2/4/8 (programmable)  
- Auto precharge / All bank precharge controlled by A10  
- 4096 ref resh cycles /64ms  
- Auto ref resh and Self ref resh  
- Row address A0-11 / Column address A0-9  
- SSTL_2 Interf ace  
184pin  
92pin  
- Module 1bank Conf igration  
- Burst Ty pe - sequential/interleav e(programmable)  
- Commands entered on each positiv e CLK edge  
APPLICATION  
Main memory unit for PC, PCserver  
MIT-DS-0397-1.1  
24.Nov.2000  
MITSUBISHI ELECTRIC  
1

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