Datasheet > MEC1701-K-BSZ-TR

MEC1701-K-BSZ-TR

更新时间： 2024-11-22 02:24:11

品牌	Logo	应用领域
美国微芯 - MICROCHIP		PC
页数	文件大小	规格书
662页	6373K
描述
Keyboard and Embedded Controller for Notebook PC

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中文翻译

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数据手册

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MEC1701-K-BSZ-TR 数据手册

MEC170x

Keyboard and Embedded Controller for Notebook PC

- Single byte read/write access

- 32 Byte page size

- 1,000,000 write cycle endurance

• GPIO and Core Logic supports 3.3V and 1.8V

Operation.

• Analog and PLL are 3.3V Operation only.

• ACPI Compliant

• LPC Interface

- Supports LPC Bus frequencies of 19MHz to

33MHz

• VTR (standby) and VBAT Power Planes

Low Standby Current in Sleep Mode

- 1.8V and 3.3V Support

• Configuration Register Set

- LPC I/O Cycles Decoded

- LPC Memory Cycles Decoded

- Clock Run Support

- Serial IRQ

- ACPI SCI interface

- Compatible with ISA Plug-and-Play Standard

- EC-Programmable Base Address

• ARM^®Cortex^®-M4 Processor Core

- 32-Bit ARM v7-M Instruction Set Architecture

- Hardware Floating Point Unit (FPU)

- Single 4GByte Addressing Space (Von Neu-

mann Model)

- SMI# output

• Enhanced Serial Peripheral Interface (eSPI)

- Intel eSPI Specification compliant

- Supports four channels/interfaces:

- Peripheral channel Interface

- Virtual Wire Interface

- Out of Band Channel Interface

- Flash Channel Interface

- Supports EC Bus Master to Host Memory

• Legacy Support

- Fast GATEA20 and Fast CPU_RESET

• System to EC Message Interface

- 8042 Style Host Interface

- ACPI Embedded Controller Interface

- Five Instances

- 1 or 4 Byte Data transfer capable

- Full-duplex Register Access

- ACPI Power Management Interface

- SCI Event-Generating Functions

- Mailbox Registers Interface

- Thirty-two 8-Bit Scratch Registers

- Two Register Mailbox Command Interface

- Two Register SMI Source Interface

- Three Embedded Memory Interface

Instances

- Little-Endian Byte Ordering

- Bit-Banding Feature Included

- NVIC Nested Vectored Interrupt Controller

- Up to 240 Individually-Vectored Interrupt Sources

Supported

- 8 Levels of Priority, Individually Assignable By Vector

- Chip-Level Interrupt Aggregator supported, to

expand number of interrupt sources or reduce

number of vectors

- System Tick Timer

- Complete ARM-Standard Debug Support

- JTAG-Based DAP Port, Comprised of SWJ-DP and

AHB-AP Debugger Access Functions

- Full DWT Hardware Functionality: 4 Data

Watchpoints and Execution Monitoring

- Full FPB Hardware Breakpoint Functionality: 6

Execution Breakpoints and 2 Literal (Data)

Breakpoints

- Comprehensive ARM-Standard Trace Sup-

port

- Full DWT Hardware Trace Functionality for

Watchpoint and Performance Monitoring

- Full ITM Hardware Trace Functionality for

Instrumented Firmware Support and Profiling

- Full ETM Hardware Trace Functionality for

Instruction Trace

- Host Serial or Parallel IRQ Source

- Provides Two Windows to On-Chip SRAM for Host

Access

- Full TPIU Functionality for Trace Output

Communication

- MPU Feature

- Two Register Mailbox Command Interface

- Host Access of Virtual Registers Without EC

Intervention

- 1µS Delay Register

• Internal Memory

- 64k Boot ROM

- Two blocks of SRAM, totaling 256KB, 320KB

• Battery Backed Resources

- Power-Fail Status Register

- 32 KHz Clock Generator

- Week Alarm Timer Interface

- Real Time Clock

or 480KB

- Each block can be used for either program or data

- One block 32KB or 64KB

- One block 224KB, 288KB or 416KB

- 128 Bytes Battery Powered SRAM

- Non-volatile Read/Write Memory

- 2KB of EEPROM

- VBAT-Powered Control Interface

- Five Wake-up Input Signals

- Optional Latching of Wake-up Inputs

- VBAT-Backed 128 Byte Memory

 2016-2020 Microchip Technology Inc.

DS00002206H-page 1

12 3 4 5 6 7...662

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