5秒后页面跳转
MDU28C-100 PDF预览

MDU28C-100

更新时间: 2024-11-17 22:30:19
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
4页 50K
描述
DUAL, HCMOS-INTERFACED FIXED DELAY LINE

MDU28C-100 数据手册

 浏览型号MDU28C-100的Datasheet PDF文件第2页浏览型号MDU28C-100的Datasheet PDF文件第3页浏览型号MDU28C-100的Datasheet PDF文件第4页 
MDU28C  
Ò
DUAL, HCMOS-INTERFACED  
FIXED DELAY LINE  
(SERIES MDU28C)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
N/C  
O1  
N/C  
N/C  
N/C  
O2  
I1  
N/C  
N/C  
N/C  
I2  
N/C  
VDD  
8
I1  
N/C  
I2  
1
2
3
4
·
·
·
·
·
·
Two independent delay lines  
Fits standard 8-pin DIP socket  
Low profile  
O1  
7
N/C  
6
Auto-insertable  
8
GND  
O2  
5
GND  
Input & outputs fully CMOS interfaced & buffered  
10 T2L fan-out capability  
MDU28C-xx  
DIP  
Military SMD  
MDU28C-xxA1 Gull-Wing  
MDU28C-xxB1 J-Lead  
MDU28C-xxMD1  
MDU28C-xxMD4  
MDU28C-xxM Military DIP  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
I1-I2  
Signal Inputs  
The MDU28C-series device is a 2-in-1 digitally buffered delay line. The  
signal inputs (I1-I2) are reproduced at the outputs (O1-O2), shifted in time  
by an amount determined by the device dash number (See Table). The  
delay lines function completely independently of each other.  
O1-O2 Signal Outputs  
VDD +5 Volts  
GND Ground  
DASH NUMBER SPECIFICATIONS  
SERIES SPECIFICATIONS  
Part  
Number  
Delay Per  
Line (ns)  
10 ± 2.0  
12 ± 2.0  
16 ± 2.0  
20 ± 2.0  
25 ± 2.0  
30 ± 2.0  
35 ± 2.0  
40 ± 2.0  
45 ± 2.2  
50 ± 2.5  
60 ± 3.0  
75 ± 3.7  
100 ± 5.0  
·
·
·
·
Minimum input pulse width: 100% of total delay  
Output rise time: 8ns typical  
Supply voltage: 5VDC ± 5%  
Supply current: ICCL = 40ma typical  
ICCH = 45ma typical  
Operating temperature: 0° to 70° C  
Temp. coefficient of total delay: 300 PPM/°C  
MDU28C-10  
MDU28C-12  
MDU28C-16  
MDU28C-20  
MDU28C-25  
MDU28C-30  
MDU28C-35  
MDU28C-40  
MDU28C-45  
MDU28C-50  
MDU28C-60  
MDU28C-75  
MDU28C-100  
·
·
O1  
100%  
I1  
O2  
100%  
I2  
NOTE: Any dash number between 10 and 100  
not shown is also available.  
VDD  
GND  
Functional block diagram  
Ó1997 Data Delay Devices  
Doc #97040  
12/12/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

与MDU28C-100相关器件

型号 品牌 获取价格 描述 数据表
MDU28C-100A1 ETC

获取价格

DUAL, HCMOS-INTERFACED FIXED DELAY LINE
MDU28C-100B1 ETC

获取价格

DUAL, HCMOS-INTERFACED FIXED DELAY LINE
MDU28C-100M ETC

获取价格

DUAL, HCMOS-INTERFACED FIXED DELAY LINE
MDU-28C-100MD1 DATADELAY

获取价格

Active Delay Line, 2-Func, 1-Tap, True Output, CMOS,
MDU28C-100MD1 DATADELAY

获取价格

ACTIVE DELAY LINE, TRUE OUTPUT, DFP14, LOW PROFILE, SMD-14
MDU28C-100MD4 ETC

获取价格

DUAL, HCMOS-INTERFACED FIXED DELAY LINE
MDU28C-10A1 DATADELAY

获取价格

Active Delay Line, 2-Func, 1-Tap, True Output,
MDU28C-10B1 DATADELAY

获取价格

Active Delay Line, 2-Func, 1-Tap, True Output,
MDU28C-10M ETC

获取价格

DUAL, HCMOS-INTERFACED FIXED DELAY LINE
MDU-28C-10MD1 DATADELAY

获取价格

Active Delay Line, 2-Func, 1-Tap, True Output, CMOS,