PIN CONNECTIONS
Table 1. 33927 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Pin Name Pin Function
Formal Name
Definition
Active low input logic signal enables the High-Side Driver for Phase A
Active high input logic signal enables the Low-Side Driver for Phase A
VDD regulator output. Internally generated 5V supply
Active low input logic signal enables the High-Side Driver for Phase B
Active high input logic signal enables the Low-Side Driver for Phase B
Interrupt pin output
12
13
PA_HS
PA_LS
VDD
Digital Input
Digital Input
Analog Output
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Phase A High-Side
Phase A Low-Side
VDD Regulator
Phase B High-Side
Phase B Low-Side
Interrupt
14
15
PB_HS
PB_LS
INT
16
17
Chip Select input. It frames SPI commands and enables SPI port
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
Clock for SPI port and typically is 3.0 MHz
18
CS
Chip Select
19
SI
Serial In
20
SCLK
SO
Serial Clock
Output data for SPI port. Tri-state until CS becomes low
Active high input logic signal enables the Low-Side Driver for Phase C
Active low input logic signal enables the High-Side Driver for Phase C
Output of the current-sensing amplifier
21
Serial Out
22
PC_LS
PC_HS
Phase C Low-Side
Phase C High-Side
Amplifier Output
Amplifier Invert
Amplifier Non-Invert
Overcurrent Out
23
24
AMP_OUT Analog Output
Inverting input of the current-sensing amplifier
25
AMP_N
AMP_P
OC_OUT
OC_TH
VSS
Analog Input
Analog Input
Digital Output
Non-inverting input of the current-sensing amplifier
Totem pole digital output of the Over-current Comparator
Threshold of the overcurrent detector
26
27
28
Analog Input Overcurrent Threshold
Ground reference for logic interface and power supplies
Substrate and ESD reference, connect to VSS
29
Ground
Ground
Voltage Source Supply
Ground
30, 31
32
GND
VLS Regulator connection for additional output capacitor, providing low
impedance supply source for Low-Side Gate Drive
VLS_CAP Analog Output VLS Regulator Output
Capacitor
Gate current return for the Low-Side FETs for Phase C gate current
Gate drive output for Phase C Low-Side
34
35
PGNDC
Power Input
Phase C Return
PC_LS_G Power Output PhaseCLow-SideGate
Drive
Source connection for Phase C High-Side FET
Gate Drive for output Phase C High-Side FET
36
37
PC_HS_S
Power Input
Phase C High-Side
Source
PC_HS_G Power Output Phase C High-Side
Gate Drive
Bootstrap capacitor for Phase C
38
39
40
PC_BOOT Analog Input
PGNDB Power Input
Phase C Bootstrap
Phase B Return
Gate current return for the Low-Side FETs for Phase B
Gate Drive for output Phase B Low-Side
PB_LS_G Power Output Phase B Low-Side Gate
Drive
Source connection for Phase B High-Side FET
Gate Drive for output Phase B High-Side
41
42
PB_HS_S
Power Input
Phase B High-side
Source
PB_HS_G Power Output Phase B High-Side
Gate Drive
Bootstrap capacitor for Phase B
43
44
45
PB_BOOT
PGNDA
Analog Input
Power Input
Phase B Bootstrap
Phase A Return
Gate current return for the Low-Side FETs for Phase A
Gate Drive for output Phase A Low-Side
PA_LS_G Power Output Phase A Low-Side Gate
Drive
33927
Analog Integrated Circuit Device Data
Freescale Semiconductor
4