Datasheet > MCP2517FDT-H/JHA

MCP2517FDT-H/JHA

更新时间： 2024-02-26 17:52:41

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
98页	1066K
描述
External CAN FD Controller with SPI Interface

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中文翻译

获取价格

数据手册

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MCP2517FDT-H/JHA 数据手册

MCP2517FD

External CAN FD Controller with SPI Interface

Oscillator Options

Features

• 40, 20 or 4 MHz crystal, or ceramic resonator; or

external clock input

General

• External CAN FD Controller with SPI Interface

• Arbitration Bit Rate up to 1 Mbps

• Data Bit Rate up to 8 Mbps

• Clock output with prescaler

SPI Interface

• Up to 20 MHz SPI clock speed

• Supports SPI modes 0,0 and 1,1

• CAN FD Controller modes

- Mixed CAN 2.0B and CAN FD mode

- CAN 2.0B mode

• Registers and bit fields are arranged in a way to

enable efficient access via SPI

• Conforms to ISO 11898-1:2015

Safety Critical Systems

Message FIFOs

• SPI commands with CRC to detect noise on SPI

interface

• 31 FIFOs, configurable as transmit or receive

FIFOs

• Error Correction Code (ECC) protected RAM

• One Transmit Queue (TXQ)

Additional Features

• Transmit Event FIFO (TEF) with 32 bit time stamp

• GPIO pins: INT0 and INT1 can be configured as

general purpose I/O

Message Transmission

• Message transmission prioritization:

- Based on priority bit field, and/or

• Open drain outputs: TXCAN, INT, INT0, and INT1

pins can be configured as push/pull or open drain

outputs

- Message with lowest ID gets transmitted first

using the Transmit Queue (TXQ)

Package Types

• Programmable automatic retransmission

attempts: unlimited, 3 attempts or disabled

MCP2517FD

SOIC14

Message Reception

•

32 Flexible Filter and Mask Objects

TXCAN

RXCAN

CLKO/SOF

INT

VDD

• Each object can be configured to filter either:

- Standard ID + first 18 data bits, or

- Extended ID

nCS

SDO

SDI

• 32-bit Time Stamp

OSC2

SCK

OSC1

INT0/GPIO0/XSTBY

INT1/GPIO1

Special Features

VSS

• VDD: 2.7 to 5.5V

• Active current: max. 20 mA at 5.5 V, 40 MHz CAN

clock

MCP2517FD

VDFN14 with wettable flanks*

• Sleep current: 10 µA, typical

TXCAN

RXCAN

CLKO/SOF

INT

VDD

• Message objects are located in RAM: 2 KB

• Up to 3 configurable interrupt pins

• Bus Health Diagnostics and Error counters

• Transceiver standby control

nCS

SDO

EP*

SDI

OSC2

OSC1

VSS

SCK

• Start of frame pin for indicating the beginning of

messages on the bus

INT0/GPIO0/XSTBY

INT1/GPIO1

• Temperature ranges:

- High (H): –40°C to +150°C

*VDFN14 includes an Exposed Thermal Pad (EP); see

Table 1-1

 2017-2018 Microchip Technology Inc.

DS20005688B-page 1

12 3 4 5 6 7...98

中文翻译

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