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MCP25025I/P PDF预览

MCP25025I/P

更新时间： 2024-02-14 03:13:17
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
66页 1110K
描述
CAN I/O Expander Family

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MCP25025I/P 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：SOIC
包装说明：SOP, SOP14,.25针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.07
JESD-30 代码：R-PDSO-G14JESD-609代码：e3
长度：8.65 mm湿度敏感等级：1
位数：8端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Parallel IO Port
最大供电电压：5.5 V最小供电电压：2.7 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.9 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

MCP25025I/P 数据手册

 浏览型号MCP25025I/P的Datasheet PDF文件第4页浏览型号MCP25025I/P的Datasheet PDF文件第5页浏览型号MCP25025I/P的Datasheet PDF文件第6页浏览型号MCP25025I/P的Datasheet PDF文件第8页浏览型号MCP25025I/P的Datasheet PDF文件第9页浏览型号MCP25025I/P的Datasheet PDF文件第10页 
MCP2502X/5X  
REGISTER 2-1:  
TEC - TRANSMITTER ERROR COUNTER  
R-0  
R-0  
R-0  
R-0  
R-0  
R-0  
R-0  
R-0  
TEC7  
TEC6  
TEC5  
TEC4  
TEC3  
TEC2  
TEC1  
TEC0  
bit 7  
bit 0  
bit 7-0  
TEC7:TEC0: Transmit Error Counter bits  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
- n = Value at POR  
REGISTER 2-2:  
REC - RECEIVER ERROR COUNTER  
R-0  
R-0  
R-0  
R-0  
R-0  
R-0  
R-0  
R-0  
REC7  
REC6  
REC5  
REC4  
REC3  
REC2  
REC1  
REC0  
bit 7  
bit 0  
bit 7-0  
REC7:REC0: Receive Error Counter bits  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
- n = Value at POR  
FIGURE 2-3:  
BIT TIME PARTITIONING  
Input Signal  
Prop  
Segment  
Phase  
Segment 1  
Phase  
Segment 2  
Sync  
Sample Point  
TQ  
nominal bit time is calculated by programming the TQ  
length and the number of TQ in each time segment, as  
discussed below.  
2.4  
Bit Timing Logic  
The Bit Timing Logic (BTL) monitors the bus line input  
and handles the bus-related bit timing based on the  
CAN protocol. The BTL synchronizes on a recessive-  
to-dominant bus transition at Start-of-Frame (hard  
synchronization) and on any further recessive-to-  
dominant bus line transition if the CAN controller itself  
does not transmit a dominant bit (resynchronization).  
The BTL also provides programmable time segments  
to compensate for the propagation delay time, phase  
shifts and to define the position of the sample point  
within the bit time. These programmable segments are  
made up of integer units called Time Quanta (TQ). The  
2.4.1  
TIME QUANTUM (TQ)  
Time Quantum is a fixed unit of time derived from the  
oscillator period. There is a programmable baud rate  
prescaler (BRP) (with integral values ranging from 1 to  
64) as well as a fixed division by two for clock  
generation.  
© 2007 Microchip Technology Inc.  
DS21664D-page 7  
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