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MCP25025I/P

更新时间： 2024-01-01 11:59:25
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
66页 1110K
描述
CAN I/O Expander Family

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MCP25025I/P 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：SOIC
包装说明：SOP, SOP14,.25针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.07
JESD-30 代码：R-PDSO-G14JESD-609代码：e3
长度：8.65 mm湿度敏感等级：1
位数：8端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Parallel IO Port
最大供电电压：5.5 V最小供电电压：2.7 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.9 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

MCP25025I/P 数据手册

 浏览型号MCP25025I/P的Datasheet PDF文件第3页浏览型号MCP25025I/P的Datasheet PDF文件第4页浏览型号MCP25025I/P的Datasheet PDF文件第5页浏览型号MCP25025I/P的Datasheet PDF文件第7页浏览型号MCP25025I/P的Datasheet PDF文件第8页浏览型号MCP25025I/P的Datasheet PDF文件第9页 
MCP2502X/5X  
2.1  
CAN Protocol Finite State Machine  
2.3  
Error Management Logic  
The heart of the engine is the Finite State Machine  
(FSM). This state machine sequences through  
messages on a bit-by-bit basis, changing states as the  
fields of the various frame types are transmitted or  
received. The FSM is a sequencer controlling the  
sequential data stream between the TX/RX Shift  
register, the CRC register and the bus line. The FSM  
also controls the Error Management Logic (EML) and  
the parallel data stream between the TX/RX Shift  
registers and the buffers. The FSM insures that the pro-  
cesses of reception, arbitration, transmission and error  
signaling are performed according to the CAN protocol.  
The automatic retransmission of messages on the bus  
line is also handled.  
The error management logic is responsible for the fault  
confinement of the CAN device. Its two counters (the  
Receive Error Counter (REC) and the Transmit Error  
Counter (TEC)) are incremented and decremented by  
commands from the Bit Stream processor. According to  
the values of the error counters, the MCP2502X/5X is  
set into the states error-active, error-passive or bus-off.  
Error-active: Both error counters are below the error-  
passive limit of 128.  
Error-passive: At least one of the error counters (TEC  
or REC) equals or exceeds 128.  
Bus-off: The transmit error counter (TEC) equals or  
exceeds the bus-off limit of 256. The device remains in  
this state until the bus-off recovery sequence is  
received. The bus-off recovery sequence consists of  
128 occurrences of 11 consecutive recessive bits.  
2.2  
Cyclic Redundancy Check (CRC)  
The Cyclic Redundancy Check register generates the  
Cyclic Redundancy Check (CRC) code that is  
transmitted after either the Control field (for messages  
with 0 data bytes) or the Data field and is used to check  
the CRC field of incoming messages.  
Note: The MCP2502X/5X, after going bus-off,  
will recover back to error-active  
automatically if the bus remains idle for  
128 x 11 bits. OPTREG2.ERRE must be  
set to force the MCP2502X/5X to enter  
Listen-only mode instead of Normal mode  
during bus recovery. The current error  
mode (except for bus-off) of the  
MCP2502X/5X can be determined by  
reading the EFLG register via the Read  
CAN error message.  
FIGURE 2-2:  
ERROR MODES STATE DIAGRAM  
RESET  
Error-Active  
REC < 127 or  
TEC < 127  
128 occurrences of  
11 consecutive  
“recessive” bits  
REC > 127 or  
TEC > 127  
Error-Passive  
TEC > 255  
Bus-Off  
DS21664D-page 6  
© 2007 Microchip Technology Inc.  
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