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MCP23S18T-E/SP PDF预览

MCP23S18T-E/SP

更新时间: 2024-02-13 03:16:57
品牌 Logo 应用领域
美国微芯 - MICROCHIP 并行IO端口微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
56页 736K
描述
16-Bit I/O Expander with Open-Drain Outputs

MCP23S18T-E/SP 技术参数

生命周期:Active零件包装代码:DIP
包装说明:0.300 INCH, LEAD FREE, PLASTIC, SDIP-28针数:28
Reach Compliance Code:compliant风险等级:5.75
Is Samacsys:NJESD-30 代码:R-PDIP-T28
长度:34.671 mmI/O 线路数量:16
端口数量:2端子数量:28
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压:5.5 V最小供电电压:1.8 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

MCP23S18T-E/SP 数据手册

 浏览型号MCP23S18T-E/SP的Datasheet PDF文件第7页浏览型号MCP23S18T-E/SP的Datasheet PDF文件第8页浏览型号MCP23S18T-E/SP的Datasheet PDF文件第9页浏览型号MCP23S18T-E/SP的Datasheet PDF文件第11页浏览型号MCP23S18T-E/SP的Datasheet PDF文件第12页浏览型号MCP23S18T-E/SP的Datasheet PDF文件第13页 
MCP23018/MCP23S18  
2. The 3-bit address is latched after tADDRLAT  
1.4  
Multi-bit Address Decoder  
.
3. The module powers down after the first rising  
edge of the serial clock is detected (tADDIS).  
The ADDR pin is used to set the slave address of the  
MCP23018 (I2C only) to allow up to eight devices on  
the bus using only a single pin. Typically, this would  
require three pins.  
Once the address bits are latched, the device will keep  
the slave address until a POR or reset condition  
occurs.  
The multi-bit Address Decoder employs a basic FLASH  
ADC architecture (Figure 1-4). The seven comparators  
generate 8 unique values based on the analog input.  
This value is converted to a 3-bit code which corre-  
sponds to the address bits (A2, A1, A0) in the serial  
OPCODE.  
1.4.1  
CALCULATING VOLTAGE ON ADDR  
When calculating the required voltage on the ADDR pin  
(V2), the set point should be the mid-point of the LSb of  
the ADC.  
The examples in Figure 1-2 and Figure 1-3 show how  
to determine the mid point voltage (V2) and the range  
of voltages based on a voltage divider circuit. The  
maximum tolerance is 20%, however, it is recom-  
mended to use 5% tolerance worst case (10% total tol-  
erance).  
Sequence of Operation (see Figure 1-5 for  
timings):  
1. Upon power up (after VDD stabilizes) the module  
becomes active after time tADEN. Note, the ana-  
log value on the ADDR pin must be stable  
before this point to ensure accurate address  
assignment.  
FIGURE 1-2:  
VOLTAGE DIVIDER EXAMPLE  
VDD  
VDD  
ADDR  
MCP23018  
A0  
A1  
A2  
R1  
V2  
R2  
VSS  
VSS  
DS22103A-page 10  
© 2008 Microchip Technology Inc.  

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