MCP23018/MCP23S18
modes explained here relate to the device’s internal
address pointer and whether or not it is incremented
after each byte is clocked on the serial interface.
1.2
Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in the
electrical specification section.
Byte Mode disables automatic address pointer incre-
menting. When operating in Byte Mode, the
MCP23X18 does not increment its internal address
counter after each byte during the data transfer. This
gives the ability to continually access the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes or for continually writing to the output
latches.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
1.3
Serial Interface
A special mode (Byte Mode with IOCON.BANK = 0)
causes the address pointer to toggle between associ-
ated A/B register pairs. For example, if the BANK bit is
cleared and the address pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note, the address
pointer can initially point to either address in the regis-
ter pair.
This block handles the functionality of the I2C
(MCP23018) or SPI (MCP23S18) interface protocol.
The MCP23X18 contains twenty two (22) individual
registers (eleven [11] register pairs) which can be
addressed through the Serial Interface block (Table 1-
1).
TABLE 1-1:
Address
REGISTER ADDRESSES
Address
Sequential Mode enables automatic address pointer
incrementing. When operating in Sequential Mode, the
MCP23X18 increments its address counter after each
byte during the data transfer. The address pointer auto-
matically rolls over to address 00h after accessing the
last register.
Access to:
IOCON.BANK = 1 IOCON.BANK = 0
00h
10h
01h
11h
02h
12h
03h
13h
04h
14h
05h
15h
06h
16h
07h
17h
08h
18h
09h
19h
0Ah
1Ah
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
IODIRA
IODIRB
IPOLA
These two modes are not to be confused with single
writes/reads and continuous writes/reads which are
serial protocol sequences. For example, the device
may be configured for Byte Mode and the master may
IPOLB
GPINTENA
GPINTENB
DEFVALA
DEFVALB
INTCONA
INTCONB
IOCON
perform
a continuous read. In this case, the
MCP23X18 would not increment the address pointer
and would repeatedly drive data from the same loca-
tion.
2
1.3.2
I C INTERFACE
IOCON
2
1.3.2.1
I C Write Operation
GPPUA
GPPUB
INTFA
The I2C write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23018. The operation is ended with a stop (P)
or restart (SR) condition being generated by the mas-
ter.
INTFB
INTCAPA
INTCAPB
GPIOA
Data is written to the MCP23018 after every byte trans-
fer. If a stop or restart condition is generated during a
data transfer, the data will not be written to the
MCP23018.
GPIOB
OLATA
OLATB
Both “byte mode” and “sequential mode” are supported
by the MCP23018. If sequential mode is enabled
(default), the MCP23018 increments its address
counter after each ACK during the data transfer.
1.3.1
BYTE MODE AND SEQUENTIAL
MODE
The MCP23X18 has the ability to operate in “Byte
Mode” or “Sequential Mode” (IOCON.SEQOP). Byte
mode and sequential mode are not to be confused with
I2C byte operations and sequential operations. The
© 2008 Microchip Technology Inc.
DS22103A-page 7
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