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MCM6323ATS12AR PDF预览

MCM6323ATS12AR

更新时间: 2023-01-02 19:50:16
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器光电二极管
页数 文件大小 规格书
10页 177K
描述
64KX16 STANDARD SRAM, 12ns, PDSO44, TSOP2-44

MCM6323ATS12AR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2,
针数:44Reach Compliance Code:unknown
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:12 ns
JESD-30 代码:R-PDSO-G44JESD-609代码:e0
长度:18.41 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端口数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mm

MCM6323ATS12AR 数据手册

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Order this document  
by MCM6323A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6323A  
Product Preview  
64K x 16 Bit 3.3 V Asynchronous  
Fast Static RAM  
The MCM6323A is a 1,048,576 bit static random access memory organized  
as 65,536 words of 16 bits. Static design eliminates the need for external clocks  
or timing strobes; CMOS circuitry reduces power consumption and provides for  
greater reliability.  
The MCM6323A is equipped with chip enable (E), write enable (W), and output  
enable (G) pins, allowing for greater system flexibility and eliminating bus con-  
tention problems. Separate byte enable controls (LB and UB) allow individual  
bytes to be written and read. LB controls the 8 DQa bits, while UB controls the  
8 DQb bits.  
YJ PACKAGE  
400 MIL SOJ  
CASE 919–01  
TS PACKAGE  
44–LEAD  
TSOP TYPE II  
CASE 924A–02  
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack-  
age and a 44–lead TSOP Type II package in copper leadframe for optimum  
printed circuit board (PCB) reliability.  
PIN ASSIGNMENT  
A
A
A
A
A
E
1
2
3
4
5
6
44  
43  
42  
41  
40  
39  
A
Single 3.3 V ± 0.3 V Power Supply  
Fast Access Time: 10, 12, 15 ns  
Equal Address and Chip Enable Access Time  
All Inputs and Outputs are TTL Compatible  
Data Byte Control  
A
A
G
UB  
LB  
Fully Static Operation  
DQa  
DQa  
DQa  
DQa  
7
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
DQb  
DQb  
DQb  
DQb  
Power Operation: 140/135/130 mA Maximum, Active AC  
Industrial Temperature Option: – 40 to + 85°C  
Part Number: SCM6323AYJ10A  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
BLOCK DIAGRAM  
V
V
V
DD  
SS  
V
SS  
DD  
OUTPUT  
ENABLE  
BUFFER  
G
HIGH BYTE OUTPUT ENABLE  
LOW BYTE OUTPUT ENABLE  
DQa  
DQa  
DQa  
DQa  
W
DQb  
DQb  
DQb  
DQb  
NC  
A
HIGH  
BYTE  
OUTPUT  
BUFFER  
7
DQb  
8
8
8
ADDRESS  
BUFFERS  
A
9
ROW  
COLUMN  
16  
DECODER DECODER  
A
HIGH  
BYTE  
WRITE  
DRIVER  
A
A
8
8
CHIP  
ENABLE  
BUFFER  
A
A
25  
24  
23  
E
A
A
NC  
NC  
SENSE  
AMPS  
64K x 16  
BIT  
16  
LOW  
BYTE  
OUTPUT  
BUFFER  
WRITE  
ENABLE  
BUFFER  
MEMORY  
ARRAY  
W
DQa  
8
8
8
PIN NAMES  
A . . . . . . . . . . . . . . . . . . . . . . . . Address Input  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte  
LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte  
DQa . . . . . . . . . . . . Lower Data Input/Output  
DQb . . . . . . . . . . . . Upper Data Input/Output  
LOW  
BYTE  
WRITE  
DRIVER  
8
8
LB  
UB  
BYTE  
ENABLE  
BUFFER  
HIGH BYTE WRITE ENABLE  
LOW BYTE WRITE ENABLE  
V
DD  
V
SS  
. . . . . . . . . . . . . . + 3.3 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . . No Connection  
This document contains information on a new product under development. Motorola reserves the right  
to change or discontinue this product without notice.  
REV 5  
11/4/98  
Motorola, Inc. 1998  

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