Order this document
by MCM218165BV/D
SEMICONDUCTOR
TECHNICAL DATA
1M x 16
Advance Information
MCM218165BV
16M CMOS Wide DRAM Family
EDO
EDO, 1M x 16, and 1K Refresh
1024 Cycle Refresh
The family of 16M Dynamic RAMs is fabricated using 0.4µ CMOS
high–speed silicon–gate process technology. It includes devices organized as
1,048,576 sixteen–bit words. Advanced circuit design and fine line processing
provide high performance, improved reliability, and low cost.
The MCM218165BV is designed to operate from a single 3.3 V only power
supply.
These devices are packaged in a standard 400 mil J–lead small outline
package (SOJ) and a standard 400 mil thin–small–outline package (TSOP II).
J PACKAGE
400 MIL SOJ
CASE 986B–01
•
•
•
•
•
•
•
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•
Single 3.3 V ± 0.3 V Power Supply
Extended Data Out (EDO) Page Mode Access
LVTTL–Compatible Inputs and Outputs (V
2 CAS Byte Control
RAS–Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: 16 ms
= 3.3 V)
CC
T PACKAGE
400 MIL TSOP II
CASE 985A–01
Fast Access Time (t
):
RAC
MCM218165BV–60 = 60 ns (Max)
MCM218165BV–70 = 70 ns (Max)
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•
Low Active Power Dissipation: 990/935 mW (Max)
Low Standby Power Dissipation: 1.8 mW (Max)
PIN NAMES
A0 – A9 . . . . . . . . . . . . . . . Address Input UCAS, LCAS . . Column Address Strobe
DQ1 – DQ16 . . . . . . . Data Input/Output
G . . . . . . . . . . . . . . . . . . . Output Enable
V
CC
V
SS
. . . . . . . . . . Power Supply (+ 3.3 V)
. . . . . . . . . . . . . . . . . . . . . . . . Ground
W . . . . . . . . . . . . . . . . Read/Write Enable NC . . . . . . . . . . . . . . . . . . No Connection
RAS . . . . . . . . . . . . Row Address Strobe
This document contains information on a new product. Specifications and information herein are subject to change without notice.
12/19/96
Motorola, Inc. 1996
MOTOROLA DRAM
MCM218165BV
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