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MCF54415 PDF预览

MCF54415

更新时间: 2024-11-16 02:48:59
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恩智浦 - NXP /
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61页 1257K
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MCF5441x ColdFire Microprocessor Data Sheet

MCF54415 数据手册

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Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: MCF54418  
Rev. 8, 06/2012  
MCF5441x  
MAPBGA–256  
MAPBGA–196  
12 mm x 12 mm  
17mm x 17mm  
MCF5441x ColdFire  
Microprocessor Data Sheet  
Version 4 ColdFire Core with EMAC and  
MMU  
Enhanced Secure Digital host controller for  
SD, SDHC, SDIO, MMC, and MMCplus  
cards  
Up to 385 Dhrystone 2.1 MIPS @ 250 MHz  
8 KB instruction cache and 8 KB data cache  
64 KB internal SRAM dual-ported to  
processor local bus and other crossbar switch  
masters  
Two ISO7816 smart card interfaces  
Two FlexCAN modules  
2
Six I C bus interfaces with DMA support in  
master mode  
System boot from NOR, NAND, SPI flash,  
EEPROM, or FRAM  
Crossbar switch technology (XBS) for  
concurrent access to peripherals or RAM  
from multiple bus masters  
Two synchronous serial interfaces  
Four 32-bit timers with DMA support  
Four programmable interrupt timers  
8-channel, 16-bit motor control PWM timer  
Dual 12-bit ADCs with shared input channels  
and multiple conversion trigger sources  
Dual 12-bit DACs with DMA support  
1-wire module with DMA support  
NAND flash controller  
64-channel DMA controller  
SDRAM controller supporting full-speed  
operation from a single x8 DDR2 component  
up to 250 MHz  
32-bit FlexBus external memory interface for  
RAM, ROM, MRAM, and programmable  
logic  
Real-time clock with 32-kHz oscillator, 2 KB  
standby SRAM, and battery backup supply  
input  
USB 2.0 host controller  
Up to four DMA-supported serial peripheral  
interfaces (DSPI)  
Up to ten UARTs with single-wire mode  
support  
Up to five external IRQ interrupts and 2  
external DMA request/acknowledge pairs  
Up to 16 processor local bus Rapid GPIO pins  
Up to 87 standard GPIO pins  
USB 2.0 host/device/On-the-Go controller  
8-bit single data rate ULPI port usable by the  
dedicated USB host module or the USB  
host/device/OTG module  
Dual 10/100 Ethernet MACs with hardware  
CRC checking/generation, IEEE 1588-2002  
support, and optional Ethernet switch  
CPU direct-attached hardware accelerator for  
DES, 3DES, AES, MD5, SHA-1, and  
SHA-256 algorithms  
Random number generator  
This document contains information on a new product. Specifications and information herein  
are subject to change without notice.  
© Freescale Semiconductor, Inc., 2011-2012. All rights reserved.  

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