MC9S08SC4 PDF预览

MC9S08SC4

更新时间: 2025-09-11 12:27:51
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飞思卡尔 - FREESCALE 微控制器
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MC9S08SC4 8-Bit Microcontroller Data Sheet

MC9S08SC4 数据手册

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Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: MC9S08SC4  
Rev. 4, 6/2010  
MC9S08SC4 8-Bit  
Microcontroller Data Sheet  
MC9S08SC4  
948F-01  
Breakpoint capability to allow single breakpoint setting  
during in-circuit debugging  
8-Bit HCS08 Central Processor Unit (CPU)  
Up to 40 MHz HCS08 CPU (central processor unit); up  
to 20 MHz bus frequency  
Peripherals  
HC08 instruction set with added BGND instruction  
SCI — Serial Communication Interface  
— Full-duplex non-return to zero (NRZ)  
— LIN master extended break generation  
— LIN slave extended break detection  
— Wake-up on active edge  
On-Chip Memory  
4 KB of FLASH with read/program/erase over full  
operating voltage and temperature  
256 bytes of Random-access memory (RAM)  
TPMx — Two 2-channel Timer/PWM modules (TPM1  
and TPM2)  
Power-Saving Modes  
Two very low power stop modes  
— 16-bit modulus or up/down counters  
Reduced power wait mode  
— Input capture, output compare, buffered  
edge-aligned or center-aligned PWM  
Clock Source Options  
Oscillator (XOSC) — Loop-control Pierce oscillator;  
Crystal or ceramic resonator range of 32 kHz to 38.4 kHz  
or 1 MHz to 16 MHz  
ADC — Analog to Digital Converter  
— 8-channel, 10-bit resolution  
— 2.5 μs conversion time  
— Automatic compare function  
— Temperature sensor  
Internal Clock Source (ICS) — Internal clock source  
module containing a frequency-locked loop (FLL)  
controlled by internal or external reference; precision  
trimming of internal reference allows 0.2 % resolution  
and 2.0 % deviation over temperature and voltage;  
supports bus frequencies from 2 MHz to 20 MHz.  
— Internal bandgap reference channel  
Input/Output  
12 general purpose I/O pins (GPIOs)  
System Protection  
8 interrupt pins with selectable polarity  
Watchdog computer operating properly (COP) reset with  
option to run from dedicated 1 kHz internal clock source  
or bus clock  
Hysteresis and configurable pull-up device on all input  
pins; Configurable slew rate and drive strength on all  
output pins.  
Low-voltage detection with reset or interrupt; selectable  
trip points  
Package Options  
16-TSSOP  
Illegal opcode detection with reset  
Illegal address detection with reset  
FLASH block protect  
Operating Parameters  
4.5-5.5 V operation  
Reset on loss of clock  
C,V, M temperature ranges available, covering -40 -  
125 °C operation  
Development Support  
Single-wire background debug interface  
Freescale reserves the right to change the detail specifications as may be required to permit  
improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.  

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