Datasheet > MC7HC273A

MC7HC273A

更新时间： 2024-11-15 22:28:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器时钟
页数	文件大小	规格书
7页	188K
描述
Octal D Flip-Flop with Common Clock and Reset

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MC7HC273A 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

The MC54/74HC273A is identical in pinout to the LS273. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device consists of eight D flip–flops with common Clock and Reset

inputs. Each flip–flop is loaded with a low–to–high transition of the Clock

input. Reset is asynchronous and active low.

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS and TTL

Operating Voltage Range: 2.0 to 6.0 V

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

Low Input Current: 1.0 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

•

Chip Complexity: 264 FETs or 66 Equivalent Gates

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXADW

MC74HCXXXADT

Ceramic

Plastic

SOIC

LOGIC DIAGRAM

TSSOP

PIN ASSIGNMENT

DATA

INPUTS

RESET

NONINVERTING

OUTPUTS

CLOCK

PIN 20 = V

PIN 10 = GND

RESET

GND

CLOCK

Design Criteria

Value

Units

Internal Gate Count*

FUNCTION TABLE

Inputs

Reset Clock

Output

Internal Gate Propagation Delay

Internal Gate Power Dissipation

1.5

5.0

µW

Speed Power Product

.0075

No Change

* Equivalent to a two–input NAND gate.

2/97

REV 7

3–1

Motorola, Inc. 1997

12 3 4 5 6 7

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