Datasheet > MC75HC107

MC75HC107

更新时间： 2024-11-20 22:51:23

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
5页	174K
描述
Dual J-K Flip-Flop with Reset

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数据手册

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MC75HC107 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

The MC74HC107 is identical in pinout to the LS107. The device inputs are

compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

Each flip flops negative edge clocked and has an active–low asynchro-

nous reset.

The HC107 is identical in function to the HC73, but has a different pinout.

D SUFFIX

SOIC PACKAGE

CASE 751A–03

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

Low Input Current: 1 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

ORDERING INFORMATION

MC74HCXXXN

MC74HCXXXD

Plastic

SOIC

•

Chip Complexity: 92 FETs or 23 Equivalent Gates

PIN ASSIGNMENT

LOGIC DIAGRAM

RESET 1

CLOCK 1

RESET 2

CLOCK 2

RESET 1

GND

CLOCK 2

FUNCTION TABLE

Inputs

Reset Clock

Outputs

RESET 2

PIN 14 = V

PIN 7 = GND

No Change

Toggle

No Change

10/95

REV 6

Motorola, Inc. 1995

12 3 4 5

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