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MC74HC4075N PDF预览

MC74HC4075N

更新时间: 2024-11-23 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
4页 140K
描述
Triple 3-Input OR Gate

MC74HC4075N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.8
系列:HC/UHJESD-30 代码:R-PDIP-T14
JESD-609代码:e0长度:18.86 mm
负载电容(CL):50 pF逻辑集成电路类型:OR GATE
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):35 ns认证状态:Not Qualified
座面最大高度:4.69 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC74HC4075N 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC74HC4075 is identical in pinout to the MC14075B. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
Low Input Current: 1 µA  
14  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
Chip Complexity: 42 FETs or 10.5 Equivalent Gates  
ORDERING INFORMATION  
MC74HCXXXXN  
MC74HCXXXXD  
Plastic  
SOIC  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
1
A1  
A1  
B1  
A2  
B2  
1
2
3
4
14  
13  
12  
11  
V
CC  
2
8
9
B1  
C1  
Y1  
Y2  
Y3  
C3  
B3  
A3  
3
4
5
A2  
B2  
C2  
C2  
Y2  
5
6
10  
9
Y3  
Y1  
6
Y = A + B + C  
GND  
7
8
C1  
11  
12  
13  
A3  
B3  
C3  
10  
FUNCTION TABLE  
PIN 14 = V  
CC  
PIN 7 = GND  
Inputs  
B
Output  
A
C
Y
L
H
X
X
L
X
H
X
L
X
X
H
L
H
H
H
10/95  
REV 6  
Motorola, Inc. 1995  

MC74HC4075N 替代型号

型号 品牌 替代类型 描述 数据表
TC74HC4075AP TOSHIBA

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M74HC4075B1R STMICROELECTRONICS

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74F32PC FAIRCHILD

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Quad 2-Input OR Gate

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