MC74HC390ND

更新时间： 2024-09-30 13:11:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		计数器
页数	文件大小	规格书
8页	219K
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MC74HC390ND 数据手册

SEMICONDUCTOR TECHNICAL DATA

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

High–Performance Silicon–Gate CMOS

The MC54/74HC390 is identical in pinout to the LS390. The device inputs

are compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

This device consists of two independent 4–bit counters, each composed

of a divide–by–two and a divide–by–five section. The divide–by–two and

divide–by–five counters have separate clock inputs, and can be cascaded to

implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.

Flip–flops internal to the counters are triggered by high–to–low transitions

of the clock input. A separate, asynchronous reset is provided for each 4–bit

counter. State changes of the Q outputs do not occur simultaneously

because of internal ripple delays. Therefore, decoded output signals are

subject to decoding spikes and should not be used as clocks or strobes

except when gated with the Clock of the HC390.

D SUFFIX

SOIC PACKAGE

CASE 751B–05

ORDERING INFORMATION

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXD

Ceramic

Plastic

SOIC

Low Input Current: 1 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No 7A

PIN ASSIGNMENT

•

Chip Complexity: 244 FETs or 61 Equivalent Gates

CLOCK A

RESET a

RESET b

LOGIC DIAGRAM

CLOCK B

3, 13

5, 11

1, 15

CLOCK A

COUNTER

GND

6, 10

7, 9

4, 12

2, 14

FUNCTION TABLE

CLOCK B

RESET

COUNTER

Clock

Reset

Action

Reset

÷ 2 and ÷ 5

Increment

÷ 2

PIN 16 = V

PIN 8 = GND

Increment

÷ 5

10/95

REV 6

Motorola, Inc. 1995

12 3 4 5 6 7 8

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