SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
14
High–Performance Silicon–Gate CMOS
1
The MC54/74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 4–bit binary ripple counters with
parallel outputs from each counter stage. A ÷ 256 counter can be obtained
by cascading the two binary counters.
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
1
Internal flip–flops are triggered by high–to–low transitions of the clock
input. Reset for the counters is asynchronous and active–high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393A.
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
14
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
1
ORDERING INFORMATION
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
MC54HCXXXAJ
Ceramic
Plastic
SOIC
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
TSSOP
•
Chip Complexity: 236 FETs or 59 Equivalent Gates
PIN ASSIGNMENT
LOGIC DIAGRAM
CLOCK a
RESET a
1
2
3
4
14
13
12
11
V
CC
CLOCK b
RESET b
3, 11
Q1
Q1
Q2
a
4, 10
Q2
Q3
Q4
1, 13
2, 12
Q1
b
BINARY
COUNTER
a
CLOCK
RESET
5, 9
6, 8
Q3
5
6
10
9
Q2
b
a
a
Q4
Q3
b
b
GND
7
8
Q4
PIN 14 = V
CC
PIN 7 = GND
FUNCTION TABLE
Inputs
Clock
Reset
Outputs
X
H
L
H
L
L
L
L
L
No Change
No Change
No Change
Advance to
Next State
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
REV 0
1
Motorola, Inc. 1995