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MC74HC393AD

更新时间： 2024-01-09 00:58:53
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 243K
描述
Dual 4-Stage Binary Ripple Counter

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中文翻译

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MC74HC393AD 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.28
Is Samacsys：N计数方向：UP
JESD-30 代码：R-PDIP-T14JESD-609代码：e0
负载/预设输入：NO逻辑集成电路类型：BINARY COUNTER
工作模式：ASYNCHRONOUS功能数量：2
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：2/6 V认证状态：Not Qualified
子类别：Counters表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MC74HC393AD 数据手册

 浏览型号MC74HC393AD的Datasheet PDF文件第2页浏览型号MC74HC393AD的Datasheet PDF文件第3页浏览型号MC74HC393AD的Datasheet PDF文件第4页浏览型号MC74HC393AD的Datasheet PDF文件第5页浏览型号MC74HC393AD的Datasheet PDF文件第6页浏览型号MC74HC393AD的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 632–08  
14  
14  
High–Performance Silicon–Gate CMOS  
1
The MC54/74HC393A is identical in pinout to the LS393. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This device consists of two independent 4–bit binary ripple counters with  
parallel outputs from each counter stage. A ÷ 256 counter can be obtained  
by cascading the two binary counters.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
1
Internal flip–flops are triggered by high–to–low transitions of the clock  
input. Reset for the counters is asynchronous and active–high. State  
changes of the Q outputs do not occur simultaneously because of internal  
ripple delays. Therefore, decoded output signals are subject to decoding  
spikes and should not be used as clocks or as strobes except when gated  
with the Clock of the HC393A.  
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
14  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948G–01  
14  
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
ORDERING INFORMATION  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
TSSOP  
•
Chip Complexity: 236 FETs or 59 Equivalent Gates  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
CLOCK a  
RESET a  
1
2
3
4
14  
13  
12  
11  
V
CC  
CLOCK b  
RESET b  
3, 11  
Q1  
Q1  
Q2  
a
4, 10  
Q2  
Q3  
Q4  
1, 13  
2, 12  
Q1  
b
BINARY  
COUNTER  
a
CLOCK  
RESET  
5, 9  
6, 8  
Q3  
5
6
10  
9
Q2  
b
a
a
Q4  
Q3  
b
b
GND  
7
8
Q4  
PIN 14 = V  
CC  
PIN 7 = GND  
FUNCTION TABLE  
Inputs  
Clock  
Reset  
Outputs  
X
H
L
H
L
L
L
L
L
No Change  
No Change  
No Change  
Advance to  
Next State  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
10/95  
REV 0  
Motorola, Inc. 1995  
12345678

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MC74HC393ADR2G ONSEMI

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MC74HC393ADT ONSEMI

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MC74HC393ADTR2 ONSEMI

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MC74HC393ADTR2G ONSEMI

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 		Dual 4−Stage Binary Ripple Counter High−Performance Silicon−Gate CMOS
MC74HC393AFEL ONSEMI

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 		Dual 4−Stage Binary Ripple Counter High−Performance Silicon−Gate CMOS
MC74HC393AFELG ONSEMI

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 		Dual 4−Stage Binary Ripple Counter High−Performance Silicon−Gate CMOS
MC74HC393AN MOTOROLA

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