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MC74HC390AN

更新时间： 2024-01-31 17:14:13
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器光电二极管
页数 文件大小 规格书
9页 268K
描述
Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections

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MC74HC390AN 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92计数方向：UP
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
负载/预设输入：NO工作模式：ASYNCHRONOUS
功能数量：2端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：2/6 V
认证状态：Not Qualified子类别：Counters
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL

MC74HC390AN 数据手册

 浏览型号MC74HC390AN的Datasheet PDF文件第2页浏览型号MC74HC390AN的Datasheet PDF文件第3页浏览型号MC74HC390AN的Datasheet PDF文件第4页浏览型号MC74HC390AN的Datasheet PDF文件第5页浏览型号MC74HC390AN的Datasheet PDF文件第6页浏览型号MC74HC390AN的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
÷
÷
1
High–Performance Silicon–Gate CMOS  
The MC54/74HC390A is identical in pinout to the LS390. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
This device consists of two independent 4–bit counters, each composed  
of a divide–by–two and a divide–by–five section. The divide–by–two and  
divide–by–five counters have separate clock inputs, and can be cascaded to  
implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.  
Flip–flops internal to the counters are triggered by high–to–low transitions  
of the clock input. A separate, asynchronous reset is provided for each 4–bit  
counter. State changes of the Q outputs do not occur simultaneously  
because of internal ripple delays. Therefore, decoded output signals are  
subject to decoding spikes and should not be used as clocks or strobes  
except when gated with the Clock of the HC390A.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
ORDERING INFORMATION  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No 7A  
TSSOP  
•
Chip Complexity: 244 FETs or 61 Equivalent Gates  
PIN ASSIGNMENT  
CLOCK A  
1
2
16  
15  
V
CC  
a
CLOCK A  
RESET a  
b
b
LOGIC DIAGRAM  
Q
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
RESET b  
Aa  
CLOCK B  
Q
a
Ab  
CLOCK B  
Q
÷
2
Ba  
Ca  
Da  
3, 13  
5, 11  
1, 15  
Q
Q
A
CLOCK A  
COUNTER  
Q
Q
Q
Q
Q
Bb  
Cb  
Db  
GND  
B
÷
5
6, 10  
7, 9  
4, 12  
2, 14  
Q
Q
CLOCK B  
RESET  
C
D
COUNTER  
FUNCTION TABLE  
Clock  
A
B
Reset  
Action  
X
X
H
Reset  
÷ 2 and ÷ 5  
PIN 16 = V  
CC  
PIN 8 = GND  
X
L
L
Increment  
÷ 2  
X
Increment  
÷ 5  
This document contains information on a product under development. Motorola reserves the right  
to change or discontinue this product without notice.  
10/95  
REV 0  
Motorola, Inc. 1995  
1234567...9

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