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MC74HC164A PDF预览

MC74HC164A

更新时间: 2024-02-10 12:40:42
品牌 Logo 应用领域
安森美 - ONSEMI 移位寄存器
页数 文件大小 规格书
8页 198K
描述
8-Bit Serial-Input/Parallel-Output Shift Register

MC74HC164A 数据手册

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High–Performance Silicon–Gate CMOS  
http://onsemi.com  
The MC74HC164A is identical in pinout to the LS164. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
MARKING  
DIAGRAMS  
14  
The MC74HC164A is an 8–bit, serial–input to parallel–output shift  
register. Two serial data inputs, A1 and A2, are provided so that one  
input may be used as a data enable. Data is entered on each rising edge  
of the clock. The active–low asynchronous Reset overrides the Clock  
and Serial Data inputs.  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HC164AN  
AWLYYWW  
1
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
SOIC–14  
D SUFFIX  
CASE 751A  
HC164A  
AWLYWW  
1
14  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
HC  
164A  
ALYW  
TSSOP–14  
DT SUFFIX  
CASE 948G  
1
Chip Complexity: 244 FETs or 61 Equivalent Gates  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
LOGIC DIAGRAM  
WW or W = Work Week  
3
1
2
Q
A
SERIAL  
DATA  
INPUTS  
A1  
A2  
4
DATA  
PIN ASSIGNMENT  
Q
B
5
Q
C
A1  
A2  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
V
CC  
6
PARALLEL  
DATA  
OUTPUTS  
Q
D
Q
10  
11  
12  
13  
H
Q
E
Q
A
Q
G
Q
F
Q
B
Q
F
8
9
Q
G
CLOCK  
RESET  
Q
C
Q
E
Q
H
Q
D
RESET  
CLOCK  
PIN 14 = V  
CC  
GND  
8
PIN 7 = GND  
FUNCTION TABLE  
ORDERING INFORMATION  
Inputs  
Reset Clock A1 A2  
Outputs  
Q  
H
Device  
Package  
PDIP–14  
Shipping  
Q
Q
B
A
MC74HC164AN  
2000 / Box  
55 / Rail  
L
H
H
H
X
X
X
H
D
X
X
D
H
L
L
L
No Change  
MC74HC164AD  
SOIC–14  
SOIC–14  
TSSOP–14  
TSSOP–14  
D
D
Q
Q
Q  
Q  
An  
An  
Gn  
Gn  
MC74HC164ADR2  
MC74HC164ADT  
MC74HC164ADTR2  
2500 / Reel  
96 / Rail  
D = data input  
– Q = data shifted from the preceding  
2500 / Reel  
Q
An  
Gn  
stage on a rising edge at the clock input.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 1  
MC74HC164A/D  

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